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In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 页码: 8
作者:  Hui, Yajuan;  Li, Qingzhen;  Wang, Leimin;  Liu, Cheng;  Zhang, Deming;  Miao, Xiangshui
收藏  |  浏览/下载：4/0  |  提交时间：2024/05/20
In-memory computing  majority gates  voltage-gated SOT-MRAM  Wallace tree multiplier  
Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 卷号: 31, 期号: 11, 页码: 1763-1773
作者:  Xue, Xinghua;  Liu, Cheng;  Liu, Bo;  Huang, Haitong;  Wang, Ying;  Luo, Tao;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20
Fault tolerant systems  Fault tolerance  Artificial neural networks  Convolution  Reliability  Computational modeling  Neurons  Fault-tolerance  soft errors  vulnerability analysis  winograd convolution (WG-Conv)  
Soft Error Reliability Analysis of Vision Transformers 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 页码: 11
作者:  Xue, Xinghua;  Liu, Cheng;  Wang, Ying;  Yang, Bing;  Luo, Tao;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：7/0  |  提交时间：2023/12/04
ABFT  fault-tolerance  soft errors  vision transformers (ViTs)  vulnerability analysis  
BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 卷号: 31, 期号: 1, 页码: 90-103
作者:  Li, Hongyan;  Lu, Hang;  Wang, Haoxuan;  Deng, Shengji;  Li, Xiaowei
收藏  |  浏览/下载：13/0  |  提交时间：2023/07/12
Deep learning accelerator  deep neural network (DNN)  hardware runtime pruning  
Taming Process Variations in CNFET for Efficient Last-Level Cache Design 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 卷号: 30, 期号: 4, 页码: 418-431
作者:  Xu, Dawen;  Feng, Zhuangyu;  Liu, Cheng;  Li, Li;  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07
CNTFETs  Delays  Transistors  Layout  Very large scale integration  Radio frequency  Energy consumption  nanotube field-effect transistor (CNFET)  last-level cache (LLC)  process variation (PV)  variation-aware cache  
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 卷号: 27, 期号: 8, 页码: 1851-1860
作者:  Wu, Bi;  Zhang, Beibei;  Cheng, Yuanqing;  Wang, Ying;  Liu, Dijun;  Zhao, Weisheng
收藏  |  浏览/下载：77/0  |  提交时间：2019/12/10
Error correction code (ECC)  last level cache (LLC)  reliability  spin-transfer-torque magnetoresistive random-access memory (STT-MRAM)  temperature  
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748
作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：53/0  |  提交时间：2019/12/12
Deep learning  error tolerance  neural network (NN)  timing variation  
Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 9, 页码: 2525-2537
作者:  Lu, Weina;  Hu, Yu;  Ye, Jing;  Li, Xiaowei
收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12
Computer-aided design flow  field-programmable gate arrays (FPGAs)  hotspot optimization  performance  
A New Binary-Halved Clustering Method and ERT Processor for ASSR System 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1871-1884
作者:  Chou, Chih-Hung;  Kuan, Ta-Wen;  Barma, Shovan;  Chen, Bo-Wei;  Ji, Wen;  Peng, Chih-Hsiang;  Wang, Jhing-Fa
收藏  |  浏览/下载：39/0  |  提交时间：2019/12/13
Automatic speech-speaker recognition (ASSR)  binary-halved clustering (BHC)  configurable processing element (CPE)  extraction  recognition  and training (ERT)  multichannel router (MCR)  multifeedback shift register (MFSR)  
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13
3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput