In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays

doi:10.1109/TVLSI.2024.3350151

	In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays
	Hui, Yajuan 1,2; Li, Qingzhen 1,2; Wang, Leimin 1,2; Liu, Cheng 3; Zhang, Deming 4; Miao, Xiangshui 5
	2024-01-12
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
页码	8
摘要	In-memory computing represents an efficient paradigm for high-performance computing using crossbar arrays of emerging nonvolatile devices. While various techniques have emerged to implement Boolean logic in memory, the latency of arithmetic circuits, particularly multipliers, significantly increases with bit-width. In this work, we introduce an in-memory Wallace tree multiplier based on majority gates within voltage-gated spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) crossbar arrays. By utilizing a resistance sum, the majority gate is implemented during READ operations in voltage-gated SOT-MRAM crossbar arrays, resulting in reduced read currents and improved energy efficiency. We employ a series of READ and WRITE operations to perform multiplier calculations, leveraging the fast READ and WRITE speeds of voltage-gated SOT-MRAM devices. Furthermore, the use of five-input majority gates simplifies multiplication by employing uniform logic gates and reducing logic depth, thereby lowering the operation's complexity and the total number of occupied cells. Our experimental results demonstrate that the proposed in-memory Wallace tree multipliers consume three times less energy for in-memory operations than previously reported 4 X 4 multipliers. Moreover, the proposed method reduces the delay overhead from O ( n(2) ) to O ( log2(n) ), where n represents the number of bits.
关键词	In-memory computing majority gates voltage-gated SOT-MRAM Wallace tree multiplier
DOI	10.1109/TVLSI.2024.3350151
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:001165589700001
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/38833
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Hui, Yajuan
作者单位	1.China Univ Geosci, Hubei Key Lab Adv Control & Intelligent Automation, Wuhan 430074, Peoples R China 2.China Univ Geosci, Engn Res Ctr Intelligent Technol Geoexplorat, Minist Educ, Wuhan 430074, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100080, Peoples R China 4.Beihang Univ, Sch Integrated Circuit Sci & Engn, Beijing 100191, Peoples R China 5.Huazhong Univ Sci & Technol, Sch Integrated Circuits, Wuhan 430074, Peoples R China
推荐引用方式 GB/T 7714	Hui, Yajuan,Li, Qingzhen,Wang, Leimin,et al. In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2024:8.
APA	Hui, Yajuan,Li, Qingzhen,Wang, Leimin,Liu, Cheng,Zhang, Deming,&Miao, Xiangshui.(2024).In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,8.
MLA	Hui, Yajuan,et al."In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS (2024):8.