中国科学院计算技术研究所机构知识库

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已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Soft Error Reliability Analysis of Vision Transformers 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 页码: 11 作者:  Xue, Xinghua;  Liu, Cheng;  Wang, Ying;  Yang, Bing;  Luo, Tao;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：6/0  |  提交时间：2023/12/04 ABFT  fault-tolerance  soft errors  vision transformers (ViTs)  vulnerability analysis
	BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 卷号: 31, 期号: 1, 页码: 90-103 作者:  Li, Hongyan;  Lu, Hang;  Wang, Haoxuan;  Deng, Shengji;  Li, Xiaowei 收藏  |  浏览/下载：11/0  |  提交时间：2023/07/12 Deep learning accelerator  deep neural network (DNN)  hardware runtime pruning
	Taming Process Variations in CNFET for Efficient Last-Level Cache Design 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 卷号: 30, 期号: 4, 页码: 418-431 作者:  Xu, Dawen;  Feng, Zhuangyu;  Liu, Cheng;  Li, Li;  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：23/0  |  提交时间：2022/12/07 CNTFETs  Delays  Transistors  Layout  Very large scale integration  Radio frequency  Energy consumption  nanotube field-effect transistor (CNFET)  last-level cache (LLC)  process variation (PV)  variation-aware cache
	Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 卷号: 29, 期号: 3, 页码: 472-484 作者:  Xu, Dawen;  Zhu, Ziyang;  Liu, Cheng;  Wang, Ying;  Zhao, Shuang;  Zhang, Lei;  Liang, Huaguo;  Li, Huawei;  Cheng, Kwang-Ting 收藏  |  浏览/下载：35/0  |  提交时间：2021/12/01 Neural networks  Circuit faults  Hardware  Acceleration  Reliability  Analytical models  Computational modeling  Integrated circuit reliability  reliability
	An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 卷号: 27, 期号: 8, 页码: 1851-1860 作者:  Wu, Bi;  Zhang, Beibei;  Cheng, Yuanqing;  Wang, Ying;  Liu, Dijun;  Zhao, Weisheng 收藏  |  浏览/下载：76/0  |  提交时间：2019/12/10 Error correction code (ECC)  last level cache (LLC)  reliability  spin-transfer-torque magnetoresistive random-access memory (STT-MRAM)  temperature
	Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 卷号: 27, 期号: 1, 页码: 159-172 作者:  Yin, Xunzhao;  Chen, Xiaoming;  Niemier, Michael;  Hu, Xiaobo Sharon 收藏  |  浏览/下载：80/0  |  提交时间：2019/04/03 Ferroelectric FET (FeFET)  logic-in-memory (LiM)  nonvolatile (NV) memory
	The Cat and Mouse in Split Manufacturing 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 卷号: 26, 期号: 5, 页码: 805-817 作者:  Wang, Yujie;  Chen, Pu;  Hu, Jiang;  Li, Guofeng;  Rajendran, Jeyavijayan 收藏  |  浏览/下载：37/0  |  提交时间：2019/12/10 Hardware security  placement perturbation  split manufacturing
	LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 卷号: 26, 期号: 4, 页码: 720-732 作者:  Shen, Haihua;  Tan, Huazhe;  Li, Huawei;  Zhang, Feng;  Li, Xiaowei 收藏  |  浏览/下载：51/0  |  提交时间：2019/12/10 Hardware Trojan (HT) detection  natural language processing (NLP)  n-gram language model  statistical analysis
	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748 作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：51/0  |  提交时间：2019/12/12 Deep learning  error tolerance  neural network (NN)  timing variation
	A Flexible Divide-and-Conquer MPSoC Architecture for MIMO Interference Cancellation 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2789-2802 作者:  Yuan, Luechao;  Liu, Cang;  Tang, Chuan;  Huang, Shan;  Chattopadhyay, Anupam;  Ascheid, Gerd;  Xing, Zuocheng 收藏  |  浏览/下载：37/0  |  提交时间：2019/12/12 Interference cancellation (IC)  matrix inversion  multiprocessor system-on-chip(MPSoC)  parallel processing  Tomlinson-Harashimaprecoding(THP)