Taming Process Variations in CNFET for Efficient Last-Level Cache Design

doi:10.1109/TVLSI.2021.3135502

	Taming Process Variations in CNFET for Efficient Last-Level Cache Design
	Xu, Dawen 1,2; Feng, Zhuangyu 1,2; Liu, Cheng 2; Li, Li 1,2; Wang, Ying 2; Li, Huawei 2,3; Li, Xiaowei 2
	2022-04-01
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
卷号	30 期号:4 页码:418-431
摘要	Carbon nanotube field-effect transistors (CNFETs) emerge as a promising alternative to CMOS transistors for the much higher speed and energy efficiency, which makes the technology particularly suitable for building the energy-hungry last-level cache (LLC). However, the process variations (PVs) in CNFET caused by the imperfect fabrication lead to large timing variations, and the worst case timing dramatically limits the LLC operation speed. Particularly, we observe that the CNFET-based cache latency distribution is closely related to the LLC layouts. For the two typical LLC layouts that have the CNT growth direction aligned to the cache way direction and cache set direction, respectively, we proposed variation-aware set aligned (VASA) cache and variation-aware way aligned (VAWA) cache in combination with corresponding cache optimizations, such as data shuffling and page mapping to enable low-latency cache for frequently used data. According to our experiments, the optimized LLC reduces the average access latency by 32% and 45% compared to the baseline designs on the two different CNFET layouts, respectively, while it improves the overall performance by 6% and 9%, and reduces the energy consumption by 4% and 8%, respectively. In addition, with both the architecture-induced latency variation and PV-incurred latency variation considered in a unified model, we extended the VAWA and VASA cache designs for the CNFET-based NUCA, and the proposed NUCA achieves both significant performance improvement and energy saving compared to the straightforward variation-aware NUCA.
关键词	CNTFETs Delays Transistors Layout Very large scale integration Radio frequency Energy consumption nanotube field-effect transistor (CNFET) last-level cache (LLC) process variation (PV) variation-aware cache
DOI	10.1109/TVLSI.2021.3135502
收录类别	SCI
语种	英语
资助项目	National Key Research and Development Program of China[2020YFB1600201] ; National Natural Science Foundation of China[61902375] ; National Natural Science Foundation of China[62174162] ; National Natural Science Foundation of China[61834006] ; National Natural Science Foundation of China[DOI: 10.1145/3287624.3287700]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000772426500009
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/18941
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Liu, Cheng
作者单位	1.Hefei Univ Technol, Sch Microelectron, Hefei 230009, Anhui, Peoples R China 2.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture SKLCA, Beijing 100190, Peoples R China 3.Peng Cheng Lab, Shenzhen 518055, Peoples R China
推荐引用方式 GB/T 7714	Xu, Dawen,Feng, Zhuangyu,Liu, Cheng,et al. Taming Process Variations in CNFET for Efficient Last-Level Cache Design[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2022,30(4):418-431.
APA	Xu, Dawen.,Feng, Zhuangyu.,Liu, Cheng.,Li, Li.,Wang, Ying.,...&Li, Xiaowei.(2022).Taming Process Variations in CNFET for Efficient Last-Level Cache Design.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,30(4),418-431.
MLA	Xu, Dawen,et al."Taming Process Variations in CNFET for Efficient Last-Level Cache Design".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 30.4(2022):418-431.