PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM

doi:10.1109/TVLSI.2015.2467157

	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM
	Wang, Ying 1; Han, Yinhe 1; Li, Huawei 1; Zhang, Lei 1; Cheng, Yuanqing 2; Li, Xiaowei 1
	2016-05-01
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
卷号	24 期号:5 页码:1613-1625
摘要	In 3-D-stacked memory chips, the problem of power supply integrity (PSI) is aggravating due to the additional through-silicon-via resistance and the higher current density in 3-D power delivery network. In particular, for the 3-D phase-change memory (PCM) well known for its high-amplitude programming current, IR-drop violation poses a serious threat that enforces a strict guard band of requesting concurrence, and consequently reduces the write throughput. This paper presents the implication of an IR-drop phenomenon in a 3-D PCM cube, and investigates IR-drop's impacts on write management in the PCM. From the obtained SPICE simulation results, we find that the issued writes have to meet the IR-drop constraint to be reliably processed, and then propose a PSI conscious write scheduler to improve the write performance within the constraint of the IR-drops and the power budget in the 3-D PCMcube. First, a Bloom-filter-based method is proposed to avoid the invalid write decisions for the PCM. Second, to support fine-grained write management in the cutting-edge PCM, we develop an inexpensive approach, weighted token assignment (WTA), to filter out PSI-unsafe write decisions by employing a support vector machine-based learning model. Last, a write reordering policy is proposed to cooperate with WTA and optimize the total write throughput for better memory performance. In the simulated hybrid main memory composed of both dynamic random access memory and 3-D PCM, the proposed scheduler significantly improves the write throughput.
关键词	3-D integration IR-drop phase-change memory (PCM) through-silicon-via (TSV) write throughput
DOI	10.1109/TVLSI.2015.2467157
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[61202056] ; National Natural Science Foundation of China[61376043] ; National Natural Science Foundation of China[61432017] ; National Natural Science Foundation of China[61176040] ; National Natural Science Foundation of China[61504153] ; National Natural Science Foundation of China[61221062] ; National Basic Research Program of China (973)[2011CB302503]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000375278300001
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：4[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/8534
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wang, Ying; Han, Yinhe; Li, Huawei; Zhang, Lei; Cheng, Yuanqing; Li, Xiaowei
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 2.Beihang Univ, Beijing 100191, Peoples R China
推荐引用方式 GB/T 7714	Wang, Ying,Han, Yinhe,Li, Huawei,et al. PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2016,24(5):1613-1625.
APA	Wang, Ying,Han, Yinhe,Li, Huawei,Zhang, Lei,Cheng, Yuanqing,&Li, Xiaowei.(2016).PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,24(5),1613-1625.
MLA	Wang, Ying,et al."PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24.5(2016):1613-1625.