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MRFI: An Open-Source Multiresolution Fault Injection Framework for Neural Network Processing 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 页码: 11
作者:  Huang, Haitong;  Liu, Cheng;  Xue, Xinghua;  Liu, Bo;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：3/0  |  提交时间：2024/05/20
Biological neural networks  Hardware  Reliability  Computational modeling  Neural networks  Fault tolerant systems  Fault tolerance  Fault evaluation  fault injection  fault simulation  multiresolution  neural network reliability  
Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 卷号: 31, 期号: 11, 页码: 1763-1773
作者:  Xue, Xinghua;  Liu, Cheng;  Liu, Bo;  Huang, Haitong;  Wang, Ying;  Luo, Tao;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20
Fault tolerant systems  Fault tolerance  Artificial neural networks  Convolution  Reliability  Computational modeling  Neurons  Fault-tolerance  soft errors  vulnerability analysis  winograd convolution (WG-Conv)  
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2021, 卷号: 70, 期号: 9, 页码: 1511-1525
作者:  Liang, Shengwen;  Wang, Ying;  Liu, Cheng;  He, Lei;  Li, Huawei;  Xu, Dawen;  Li, Xiaowei
收藏  |  浏览/下载：38/0  |  提交时间：2021/12/01
Neural networks  Hardware  System-on-chip  Task analysis  Feature extraction  Memory management  Graph neural network  accelerator architecture  hardware acceleration  
Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 卷号: 29, 期号: 3, 页码: 472-484
作者:  Xu, Dawen;  Zhu, Ziyang;  Liu, Cheng;  Wang, Ying;  Zhao, Shuang;  Zhang, Lei;  Liang, Huaguo;  Li, Huawei;  Cheng, Kwang-Ting
收藏  |  浏览/下载：38/0  |  提交时间：2021/12/01
Neural networks  Circuit faults  Hardware  Acceleration  Reliability  Analytical models  Computational modeling  Integrated circuit reliability  reliability  
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748
作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：53/0  |  提交时间：2019/12/12
Deep learning  error tolerance  neural network (NN)  timing variation  
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296
作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：70/0  |  提交时间：2019/12/12
Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)  
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13
3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput  
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 10, 页码: 1787-1800
作者:  Zhang, Ying;  Li, Huawei;  Min, Yinghua;  Li, Xiaowei
收藏  |  浏览/下载：63/0  |  提交时间：2019/12/16
Crosstalk  crosstalk tolerance  interconnects  network-on-chip (NOC)  
On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 卷号: 17, 期号: 9, 页码: 1173-1186
作者:  Zhang, Lei;  Han, Yinhe;  Xu, Qiang;  Li, Xiao wei;  Li, Huawei
收藏  |  浏览/下载：38/0  |  提交时间：2019/12/16
Defect tolerance  manycore system  network-on-chip  core-level redundancy  topology reconfiguration  
Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 卷号: 15, 期号: 5, 页码: 531-540
作者:  Han, Yinhe;  Hu, Yu;  Li, Xiaowei;  Li, Huawei;  Chandra, Anshuman
收藏  |  浏览/下载：38/0  |  提交时间：2019/12/16
automatic test equipment (ATE)  Godson processor  MUX network  test stimulus decompression