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Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects
Zhang, Ying; Li, Huawei; Min, Yinghua; Li, Xiaowei
2011-10-01
发表期刊IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN1063-8210
卷号19期号:10页码:1787-1800
摘要With the shrink of technology to the nanometer scale, network-on-chip (NOC) has become a reasonable solution for connecting many cores on a single chip. It suffers however from increasingly serious interconnect crosstalk effects, which constrain the overall performance of NOC systems. In this paper, a crosstalk tolerance method is proposed for reducing bus delay on NOC interconnects. Crosstalk-induced latency is predicted by analyzing the possible crosstalk effects of adjacent patterns stored in an NOC router. Transition times of selected bits are then adjusted to relieve these predicted crosstalk-induced effects. Experimental results on interconnects show that the proposed method can achieve the same bus delay reduction as the insertion of extra shielding wires into two adjacent wires, while the proposed method requires no extra wires. Compared with previous methods using a dual rail code, a crosstalk avoidance code, and/or a variable clock, the proposed approach provides a larger reduction of bus delay with less area overhead.
关键词Crosstalk crosstalk tolerance interconnects network-on-chip (NOC)
DOI10.1109/TVLSI.2010.2062201
收录类别SCI
语种英语
资助项目National Natural Science Foundation of China (NSFC)[60776031] ; National Natural Science Foundation of China (NSFC)[60633060] ; National Natural Science Foundation of China (NSFC)[60921002] ; National Basic Research Program of China (973)[2005CB321605]
WOS研究方向Computer Science ; Engineering
WOS类目Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号WOS:000293755900006
出版者IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
被引频次:5[WOS]   [WOS记录]     [WOS相关记录]
文献类型期刊论文
条目标识符http://119.78.100.204/handle/2XEOYT63/12533
专题中国科学院计算技术研究所期刊论文_英文
通讯作者Zhang, Ying
作者单位Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing 100190, Peoples R China
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Zhang, Ying,Li, Huawei,Min, Yinghua,et al. Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2011,19(10):1787-1800.
APA Zhang, Ying,Li, Huawei,Min, Yinghua,&Li, Xiaowei.(2011).Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,19(10),1787-1800.
MLA Zhang, Ying,et al."Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 19.10(2011):1787-1800.
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