中国科学院计算技术研究所机构知识库

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	Taming Process Variations in CNFET for Efficient Last-Level Cache Design 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 卷号: 30, 期号: 4, 页码: 418-431 作者:  Xu, Dawen;  Feng, Zhuangyu;  Liu, Cheng;  Li, Li;  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：30/0  |  提交时间：2022/12/07 CNTFETs  Delays  Transistors  Layout  Very large scale integration  Radio frequency  Energy consumption  nanotube field-effect transistor (CNFET)  last-level cache (LLC)  process variation (PV)  variation-aware cache
	LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2017, 卷号: E100D, 期号: 2, 页码: 323-331 作者:  Hu, Yu;  Ye, Jing;  Shi, Zhiping;  Li, Xiaowei 收藏  |  浏览/下载：55/0  |  提交时间：2019/12/12 process variation  timing variation  sample  path selection  least square
	Statistical energy optimization on voltage-frequency island based MPSoCs in the presence of process variations 期刊论文 MICROELECTRONICS JOURNAL, 2016, 卷号: 54, 页码: 23-31 作者:  Jin, Song;  Han, Yinhe;  Pei, Songwei 收藏  |  浏览/下载：40/0  |  提交时间：2019/12/13 System energy  Process variation  Voltage-frequency island  Multiprocessor system-on-chip
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586 作者:  Chen, Shuai;  Li, Hao;  Chiang, Patrick Yin 收藏  |  浏览/下载：41/0  |  提交时间：2019/12/13 All-digital clock and data recovery (ADCDR)  delay-locked loop (DLL)  forwarded-clock (FC) receiver  high-density interconnect  jitter tolerance  multicore processor  process variation  voltage and temperature drift
	Statistical lifetime reliability optimization considering joint effect of process variation and aging 期刊论文 INTEGRATION-THE VLSI JOURNAL, 2011, 卷号: 44, 期号: 3, 页码: 185-191 作者:  Jin, Song;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/16 Lifetime reliability  Process variation  NBTI  Duty cycle  Gate sizing
	Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling 期刊论文 JOURNAL OF SYSTEMS ARCHITECTURE, 2010, 卷号: 56, 期号: 10, 页码: 534-542 作者:  Dong, Jianbo;  Zhang, Lei;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei 收藏  |  浏览/下载：43/0  |  提交时间：2019/12/16 Process variation  Thread-level redundancy  Chip Multiprocessor  Scheduling
	Testable Critical Path Selection Considering Process Variation 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, 卷号: E93D, 期号: 1, 页码: 59-67 作者:  Fu, Xiang;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：42/0  |  提交时间：2019/12/16 testable critical path selection  process variation