Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling

doi:10.1016/j.sysarc.2010.09.003

	Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling
	Dong, Jianbo 1,2; Zhang, Lei 1; Han, Yinhe 1,2; Yan, Guihai 1,2; Li, Xiaowei 1,2
	2010-10-01
发表期刊	JOURNAL OF SYSTEMS ARCHITECTURE
ISSN	1383-7621
卷号	56 期号:10 页码:534-542
摘要	Thread-level redundancy is an efficient approach for transient fault detection and recovery in Chip Multiprocessors (CMPs), in which two adjacent cores are statically coupled to form a functional Dual Modular Redundancy (DMR). Manufacturing process variations cause core-to-core (C2C) performance asymmetry across the chip, which can be further divided into the asymmetry among core-pairs and the asymmetry within a core-pair. We call them inter- and intra-pair asymmetries, respectively, both of which should be taken into considerations in application scheduling for CMPs with static core coupling. In this paper, we first formulate the above scheduling problem as a 0-1 programming problem to maximize the system Weighted Throughput. An efficient IVF&AppSen algorithm is then proposed, which we prove to be optimal when the number of applications equals to that of core-pairs. We also adapt the Simulated Annealing technique to tackle this problem when applications are less than core-pairs on chip. Simulations on a 64-core CMP shows that the proposed algorithms achieve 2.5-9.3% improvement in Weighted Throughput when compared to prior VarF&AppIPC algorithm. (C) 2010 Elsevier B.V. All rights reserved.
关键词	Process variation Thread-level redundancy Chip Multiprocessor Scheduling
DOI	10.1016/j.sysarc.2010.09.003
收录类别	SCI
语种	英语
资助项目	National Basic Research Program of China (973)[2011CB302503] ; National Natural Science Foundation of China (NSFC)[60806014] ; National Natural Science Foundation of China (NSFC)[60831160526] ; National Natural Science Foundation of China (NSFC)[60633060] ; National Natural Science Foundation of China (NSFC)[60921002] ; National Natural Science Foundation of China (NSFC)[61076037] ; National Natural Science Foundation of China (NSFC)[60906018] ; Hi-Tech Research and Development Program of China (863)[2009AA01Z126]
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:000284570600005
出版者	ELSEVIER SCIENCE BV
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/12300
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Han, Yinhe
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Key Lab Comp Syst & Architecture, Beijing, Peoples R China 2.Chinese Acad Sci, Grad Univ, Beijing, Peoples R China
推荐引用方式 GB/T 7714	Dong, Jianbo,Zhang, Lei,Han, Yinhe,et al. Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling[J]. JOURNAL OF SYSTEMS ARCHITECTURE,2010,56(10):534-542.
APA	Dong, Jianbo,Zhang, Lei,Han, Yinhe,Yan, Guihai,&Li, Xiaowei.(2010).Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling.JOURNAL OF SYSTEMS ARCHITECTURE,56(10),534-542.
MLA	Dong, Jianbo,et al."Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling".JOURNAL OF SYSTEMS ARCHITECTURE 56.10(2010):534-542.