A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects

doi:10.1109/TVLSI.2015.2409987

	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
	Chen, Shuai 1; Li, Hao 2; Chiang, Patrick Yin 2,3
	2016-02-01
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
卷号	24 期号:2 页码:578-586
摘要	This paper presents a robust energy/area-efficient receiver fabricated in a 28-nm CMOS process. The receiver consists of eight data lanes plus one forwarded-clock lane supporting the hypertransport standard for high-density chip-to-chip links. The proposed all-digital clock and data recovery (ADCDR) circuit, which is well suited for today's CMOS process scaling, enables the receiver to achieve low power and area consumption. The ADCDR can enter into open loop after lock-in to save power and avoid clock dithering phenomenon. Moreover, to compensate the open loop, a phase tracking procedure is proposed to enable the ADCDR to track the phase drift due to the voltage and temperature variations. Furthermore, the all-digital delay-locked loop circuit integrated in the ADCDR can generate accurate multiphase clocks with the proposed calibrated locking algorithm in the presence of process variations. The precise multiphase clocks are essential for the half-rate sampling and Alexander-type phase detecting. Measurement results show that the receiver can operate at a data rate of 6.4 Gbits/s with a bit error rate <10(-12), consuming 7.5-mW per lane (1.2 pJ/bit) under a 0.85 V power supply. With ADCDR's phase tracking, the receiver performs better in jitter tolerance and achieves a 500-kHz bandwidth, which is high enough to track the phase drift. The receiver core occupies an area of 0.02 mm(2) per lane.
关键词	All-digital clock and data recovery (ADCDR) delay-locked loop (DLL) forwarded-clock (FC) receiver high-density interconnect jitter tolerance multicore processor process variation voltage and temperature drift
DOI	10.1109/TVLSI.2015.2409987
收录类别	SCI
语种	英语
资助项目	National Science and Technology Major Project of China[2009ZX01028-002-003] ; National Natural Science Foundation of China[61221062]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000369479500015
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：15[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/8862
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Chen, Shuai; Li, Hao; Chiang, Patrick Yin
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China 2.Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA 3.Fudan Univ, State Key Lab ASIC, Shanghai 200032, Peoples R China
推荐引用方式 GB/T 7714	Chen, Shuai,Li, Hao,Chiang, Patrick Yin. A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2016,24(2):578-586.
APA	Chen, Shuai,Li, Hao,&Chiang, Patrick Yin.(2016).A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,24(2),578-586.
MLA	Chen, Shuai,et al."A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24.2(2016):578-586.