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Path Delay Test Generation Toward Activation of Worst Case Coupling Effects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 11, 页码: 1969-1982
作者:  Zhang, Minjin;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：78/0  |  提交时间：2019/12/16
Crosstalk-induced delay  delay testing  path delay fault  signal integrity  test generation  timing analysis  
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 10, 页码: 1787-1800
作者:  Zhang, Ying;  Li, Huawei;  Min, Yinghua;  Li, Xiaowei
收藏  |  浏览/下载：75/0  |  提交时间：2019/12/16
Crosstalk  crosstalk tolerance  interconnects  network-on-chip (NOC)  
X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 卷号: 18, 期号: 7, 页码: 1081-1092
作者:  Li, Jia;  Xu, Qiang;  Hu, Yu;  Li, Xiaowei
收藏  |  浏览/下载：43/0  |  提交时间：2019/12/16
At-speed scan-based testing  low-power testing  X-filling  
Testable Critical Path Selection Considering Process Variation 期刊论文
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, 卷号: E93D, 期号: 1, 页码: 59-67
作者:  Fu, Xiang;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：44/0  |  提交时间：2019/12/16
testable critical path selection  process variation  
Co-optimization of Dynamic/Static Test Power in Scan Test 期刊论文
CHINESE JOURNAL OF ELECTRONICS, 2009, 卷号: 18, 期号: 1, 页码: 54-58
作者:  Wang Wei;  Han Yinhe;  Li Xiaowei;  Fang Fang
收藏  |  浏览/下载：45/0  |  提交时间：2019/12/16
Co-optimization  Test power  Blocking logic  Minimum leakage vector  
Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor 期刊论文
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2008, 卷号: 23, 期号: 6, 页码: 1037-1046
作者:  Wang, Da;  Hu, Yu;  Li, Hua-Wei;  Li, Xiao-Wei
收藏  |  浏览/下载：46/0  |  提交时间：2019/12/16
microprocessor design-for-testability  test generation  built-in self-test  at-speed testing