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Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 2, 页码: 603-616
作者:  Du, Yibo;  Wang, Ying;  Wang, Mengdi;  Li, Xiaowei;  Han, Yinhe
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Hardware  Chiplets  Homomorphic encryption  Polynomials  Vectors  Scheduling algorithms  Noise  Program processors  Design automation  Computational efficiency  Chiplet  fully homomorphic encryption (FHE)  hardware-software co-design  heterogeneous architecture  
LayerTEE: Decoupled Memory Protection for Scalable Multilayer Communication on RISC-V 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 1, 页码: 533-546
作者:  Pan, Shangjie;  Yang, Yinghao;  Peng, Xuanyao;  Zhao, Xiquan;  Du, Dong;  Lu, Hang;  Xia, Yubin;  Li, Xiaowei
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Cryptography  Security  Cloud computing  Scalability  Protection  Memory management  Hardware  Communication systems  Software  Program processors  Communication  memory isolation  RISC-V  trusted execution environment (TEE)  
A data-centric chip design agent framework for Verilog code generation 期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2025, 卷号: 30, 期号: 6, 页码: 27
作者:  Chang, Kaiyan;  Zhu, Wenlong;  Wang, Kun;  He, Xinyang;  Yang, Nan;  Chen, Zhirong;  Jin, Dantong;  Li, Cangyuan;  Zhou, Yunhao;  Yan, Hao;  Zhao, Zhuoliang;  Cheng, Yuan;  Wang, Mengdi;  Liang, Shengwen;  Han, Yinhe;  Li, Xiaowei;  Li, Huawei;  Wang, Ying
收藏  |  浏览/下载：2/0  |  提交时间：2026/05/25
Large language model  hardware generation  data augmentation  
GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3816-3829
作者:  Fan, Haishuang;  Meng, Rui;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：21/0  |  提交时间：2025/12/03
Field programmable gate arrays  Redundancy  Indexes  Graphics processing units  Central Processing Unit  Integrated circuit modeling  Computational modeling  Engines  Design automation  Data models  Accelerator  FPGA  Graph processing  
Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3451-3464
作者:  Fan, Haishuang;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：31/0  |  提交时间：2025/12/03
Binary sequences  Streaming media  Decoding  Artificial neural networks  Superresolution  Kernel  Engines  Design automation  Video codecs  Throughput  Accelerator  codec  FPGA  super-resolution (SR)  
DNA: A General Dynamic Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 9, 页码: 3210-3222
作者:  Liu, Lian;  Yu, Jinxin;  Wang, Mengdi;  Li, Xiaowei;  Han, Yinhe;  Wang, Ying
收藏  |  浏览/下载：21/0  |  提交时间：2025/12/03
Dynamic scheduling  Artificial neural networks  DNA  Processor scheduling  Loading  Prefetching  Runtime  Costs  Switches  Optimization  Dynamic NN  NPU design  accelerator  
Memory-Efficient and Adaptive Heterogeneous Framework for Gate-Level Fault Simulation 期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2025, 卷号: 30, 期号: 5, 页码: 27
作者:  Chao, Zhiteng;  Gu, Feng;  Huang, Junying;  Li, Wenjie;  Ye, Jing;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：25/0  |  提交时间：2025/12/03
Heterogeneous  memory-efficient  adaptive  
KPU: Kernel Processing Unit for in-Memory Analytical Query Processing 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 8, 页码: 2702-2716
作者:  Wu, Jingya;  Lu, Wenyan;  Fan, Haishuang;  Kong, Hao;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：28/0  |  提交时间：2025/12/03
Kernel  Bandwidth  Hardware  Central Processing Unit  Query processing  Programming  Parallel processing  Computers  Satellites  Database  domain-specific computer architecture  programmability  SQL  SQL  
Functional Testing and Repair for ReRAM-Based Deep-Learning Accelerators 期刊论文
IEEE DESIGN & TEST, 2025, 卷号: 42, 期号: 3, 页码: 66-73
作者:  Li, Wen;  Wang, Ying;  Li, Huawei;  Li, Xiaowei;  Zou, Kaiwei
收藏  |  浏览/下载：58/0  |  提交时间：2025/06/25
Accuracy  Fault tolerant systems  Fault tolerance  Deep learning  Image edge detection  Fault detection  Computational modeling  Training  Reliability  Hafnium  Deep Neural Network  ReRAM  Functional Test  Computing-in-Memory  
Trident: The Acceleration Architecture for High-Performance Private Set Intersection 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 4, 页码: 1152-1167
作者:  Zhang, Jinkai;  Yang, Yinghao;  Zhou, Zhe;  Hu, Zhicheng;  Zhao, Xin;  Chang, Liang;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：62/0  |  提交时间：2025/06/25
Protocols  Receivers  Cryptography  Hardware  Central Processing Unit  Random access memory  Data privacy  Polynomials  Field programmable gate arrays  Computer architecture  Private set intersection (PSI)  fully homomorphic encryption (FHE)  FPGA accelerator  privacy computing