A data-centric chip design agent framework for Verilog code generation

doi:10.1145/3727980

CSpace

	A data-centric chip design agent framework for Verilog code generation
	Chang, Kaiyan 1,2; Zhu, Wenlong 3; Wang, Kun 4; He, Xinyang 5; Yang, Nan 3; Chen, Zhirong 4; Jin, Dantong 6; Li, Cangyuan 7; Zhou, Yunhao 8; Yan, Hao 9; Zhao, Zhuoliang 8; Cheng, Yuan 10; Wang, Mengdi 3; Liang, Shengwen 1; Han, Yinhe 1; Li, Xiaowei 1,2; Li, Huawei 1,2; Wang, Ying 3
	2025-11-01
发表期刊	ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
ISSN	1084-4309
卷号	30 期号:6 页码:27
摘要	Recent advances in large language models (LLMs) have demonstrated significant potential for automated hardware description language (HDL) code generation from high-level specifications. However, two critical challenges limit further progress in this domain: the scarcity of quality Verilog training data and the inability of current approaches to generate RTL code optimized for power, performance, and area (PPA) metrics. This article presents a comprehensive data-centric framework that addresses these limitations through innovations in both pre-fine-tuning data preparation and after-fine-tuning optimization strategies. In the pre-fine-tuning phase, we tackle the data scarcity problem with an automated design-data augmentation framework that generates high-volume, high-quality natural language specifications aligned with corresponding Verilog code and EDA scripts. Our approach creates a complete RTL-level feedback loop by augmenting EDA scripts, RTL code, and EDA tool feedback. In the after-fine-tuning phase, we focus on generating PPA-aware RTL code through a novel search and prompt framework. Our approach implements iterative filtering and selection of LLM-generated Verilog variants while providing high-quality predefined prompts, including composition and interface specifications. To evaluate the effectiveness of our data augmentation method, we fine-tune Llama 2-13B and Llama 2-7B models using the dataset generated by our augmentation framework. The results demonstrate a significant improvement in the Verilog generation tasks with LLMs. Moreover, the accuracy of Verilog generation surpasses that of the current state-of-the-art open-source Verilog generation model, increasing from 58.8% to 70.6% with the same benchmark. Our 13B model has a pass rate improvement compared with GPT-3.5 in Verilog generation and outperforms in EDA script (i.e., SiliconCompiler) generation with only 200 EDA script data. Additionally, to evaluate the effectiveness of the our agent framework, we compare the PPA on the GPT-3.5, where the results show that the agent refined RTL code can have a better quality than the generated RTL code only with GPT-3.5.
关键词	Large language model hardware generation data augmentation
DOI	10.1145/3727980
收录类别	SCI
语种	英语
WOS研究方向	Computer Science
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Software Engineering
WOS记录号	WOS:001616616200005
出版者	ASSOC COMPUTING MACHINERY
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/42952
专题	中国科学院计算技术研究所
通讯作者	Chang, Kaiyan
作者单位	1.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing, Peoples R China 2.Univ Chinese Acad Sci, Beijing, Peoples R China 3.Chinese Acad Sci, Inst Comp Technol, Beijing, Peoples R China 4.Chinese Acad Sci, Inst Comp Technol, CICS, Beijing, Peoples R China 5.Univ Chinese Acad Sci, Chengdu Inst Comp Applicat, Chengdu, Peoples R China 6.Zhejiang Lab, Hangzhou, Peoples R China 7.Chinese Acad Sci, CICS, ICT, Beijing, Peoples R China 8.Shanghai Innovat Ctr Processor Technol, Shanghai, Peoples R China 9.Shanghai Univ, Shanghai, Peoples R China 10.Nanjing Univ, Nanjing, Peoples R China
推荐引用方式 GB/T 7714	Chang, Kaiyan,Zhu, Wenlong,Wang, Kun,et al. A data-centric chip design agent framework for Verilog code generation[J]. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,2025,30(6):27.
APA	Chang, Kaiyan.,Zhu, Wenlong.,Wang, Kun.,He, Xinyang.,Yang, Nan.,...&Wang, Ying.(2025).A data-centric chip design agent framework for Verilog code generation.ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS,30(6),27.
MLA	Chang, Kaiyan,et al."A data-centric chip design agent framework for Verilog code generation".ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 30.6(2025):27.