GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine

doi:10.1109/TCAD.2025.3555192

	GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine
	Fan, Haishuang 1,2; Meng, Rui 1,2; Sun, Qichu 1,2; Wu, Jingya 1; Lu, Wenyan 1,3; Li, Xiaowei 1,2; Yan, Guihai 1,3
	2025-10-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	44 期号:10 页码:3816-3829
摘要	Graphs play an important role in various applications. With the rapid expansion of vertices in real life, existing large-scale graph processing frameworks on CPUs and GPUs encounter challenges in optimizing cache usage due to irregular memory access patterns. To address this, graph reordering has been proposed to improve the locality of the graph, but introduces significant overhead without delivering substantial end-to-end performance improvement. While there have been many FPGA-based accelerators for graph processing, achieving high throughput often requires complex graph prepossessing on CPUs. Therefore, implementing an efficient end-to-end graph processing system remains challenging. This article introduces GRACE, an end-to-end FPGA-based graph processing accelerator with a graph reordering engine and a pull-based vertex-centric programming model (PL-VCPM) Engine. First, GRACE employs a customized high-degree vertex cache (HDC) to improve memory access efficiency. Second, GRACE offloads the graph preprocessing to FPGA. We customize an efficient graph reordering engine to complete preprocessing. Third, GRACE adopts a graph pruning strategy to remove the activation and computation redundancy in graph processing. Finally, GRACE introduces a graph conflict board (GCB) to resolve data conflicts and a multiport cache to enhance parallel efficiency. Experimental results demonstrate that GRACE achieves 7.1 x end-to-end performance speedup over CPU and 1.8 x over GPU, as well as 27.3 x and 8.7 x energy efficiency over CPU and GPU. Moreover, GRACE delivers up to 34.9 x performance speedup compared to the state-of-the-art FPGA accelerator.
关键词	Field programmable gate arrays Redundancy Indexes Graphics processing units Central Processing Unit Integrated circuit modeling Computational modeling Engines Design automation Data models Accelerator FPGA Graph processing
DOI	10.1109/TCAD.2025.3555192
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China (NSFC)[62090020] ; National Natural Science Foundation of China (NSFC)[92373206] ; Strategic Priority Research Program of the Chinese Academy of Sciences[XDB44030100] ; Strategic Priority Research Program of the Chinese Academy of Sciences[XDB0660100] ; Internship Program of YUSUR Technology Company Ltd.
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:001577057000019
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/41695
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Yan, Guihai
作者单位	1.Chinese Acad Sci, Inst Comp Technol, SKLP, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Sch Comp Sci & Technol, Beijing 101408, Peoples R China 3.YUSUR Technol Co Ltd, Beijing 100094, Peoples R China
推荐引用方式 GB/T 7714	Fan, Haishuang,Meng, Rui,Sun, Qichu,et al. GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2025,44(10):3816-3829.
APA	Fan, Haishuang.,Meng, Rui.,Sun, Qichu.,Wu, Jingya.,Lu, Wenyan.,...&Yan, Guihai.(2025).GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,44(10),3816-3829.
MLA	Fan, Haishuang,et al."GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 44.10(2025):3816-3829.