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PDG: A Prefetcher for Dynamic Graph Updating 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 4, 页码: 1246-1259
作者:  Zhang, Xinmiao;  Liu, Cheng;  Ni, Jiacheng;  Cheng, Yuanqing;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：13/0  |  提交时间：2024/05/20
Prefetching  Arrays  Optimization  Runtime  Heuristic algorithms  Computers  Monitoring  Computer architecture  data prefetching  memory system  
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization 期刊论文
ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2020, 卷号: 16, 期号: 3, 页码: 18
作者:  Ni, Jiacheng;  Liu, Keren;  Wu, Bi;  Zhao, Weisheng;  Cheng, Yuanqing;  Zhang, Xiaolong;  Wang, Ying
收藏  |  浏览/下载：63/0  |  提交时间：2020/12/10
STT-MRAM  write energy reductions  data patterns  cache hierarchy  
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 4, 页码: 803-815
作者:  Wu, Bi;  Dai, Pengcheng;  Cheng, Yuanqing;  Wang, Ying;  Yang, Jianlei;  Wang, Zhaohao;  Liu, Dijun;  Zhao, Weisheng
收藏  |  浏览/下载：60/0  |  提交时间：2020/12/10
System-on-chip  Computer architecture  Magnetic tunneling  Transistors  Switches  Thermal sensors  Organizations  Cache  data migration  low power  spin transfer torque magnetic memory (STT-MRAM)  thermal gradient  
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 卷号: 67, 期号: 1, 页码: 108-120
作者:  Wu, Bi;  Dai, Pengcheng;  Wang, Zhaohao;  Wang, Chao;  Wang, Ying;  Yang, Jianlei;  Cheng, Yuanqing;  Liu, Dijun;  Zhang, Youguang;  Zhao, Weisheng;  Hu, Xiaobo Sharon
收藏  |  浏览/下载：58/0  |  提交时间：2020/12/10
NAND-SPIN  spin orbit torque (SOT) MRAM  last level cache  write throughput  high performance  
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 卷号: 27, 期号: 8, 页码: 1851-1860
作者:  Wu, Bi;  Zhang, Beibei;  Cheng, Yuanqing;  Wang, Ying;  Liu, Dijun;  Zhao, Weisheng
收藏  |  浏览/下载：86/0  |  提交时间：2019/12/10
Error correction code (ECC)  last level cache (LLC)  reliability  spin-transfer-torque magnetoresistive random-access memory (STT-MRAM)  temperature  
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296
作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：78/0  |  提交时间：2019/12/12
Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)  
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：59/0  |  提交时间：2019/12/13
3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput  
无权访问的条目 学位论文
作者:  成元庆
Adobe PDF(5336Kb)  |  收藏  |  浏览/下载：0/0  |  提交时间：2012/07/26