中国科学院计算技术研究所机构知识库

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限定条件	作者：Wang, Ying    第一作者    资助项目：National Natural Science Foundation of China[61432017]

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	A QoS-QoR Aware CNN Accelerator Design Approach 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 11, 页码: 1995-2007 作者:  Wang, Ying;  Li, Huawei;  Cheng, Long;  Li, Xiaowei 收藏  |  浏览/下载：47/0  |  提交时间：2020/12/10 Approximate computing  convolutional neural network (CNN)  deep learning (DL)  quality of service (QoS)  real-time
	Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 4, 页码: 767-779 作者:  Cheng, Yun;  Li, Huawei;  Wang, Ying;  Li, Xiaowei 收藏  |  浏览/下载：78/0  |  提交时间：2019/08/16 Cluster generation  post-silicon debug  state restoration  trace signal selection
	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984 作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：68/0  |  提交时间：2019/12/10 Convolutional neural network (CNN)  deep learning  low power  memory subsystem
	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277 作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：67/0  |  提交时间：2019/12/10 Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)
	Processor Design Space Exploration via Statistical Sampling and Semi-Supervised Ensemble Learning 期刊论文 IEEE ACCESS, 2018, 卷号: 6, 页码: 25495-25505 作者:  Li, Dandan;  Yao, Shuzhen;  Wang, Ying 收藏  |  浏览/下载：46/0  |  提交时间：2019/12/10 Design space exploration  Latin hypercube sampling  adaboost  microprocessor design
	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748 作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/12 Deep learning  error tolerance  neural network (NN)  timing variation
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh
	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13 3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput
	VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：35/0  |  提交时间：2019/12/13 Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)