A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors

doi:10.1109/TCAD.2017.2729404

	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors
	Wang, Ying; Li, Huawei; Han, Yinhe; Li, Xiaowei
	2018-06-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	37 期号:6 页码:1265-1277
摘要	Data compression has been intensively studied to increase the utility of cache, network-on-chip (NoC), and main memory in energy-efficient processors. However, prior solutions to data compression often add remarkable compression and decompression delay to the critical path of memory access, which is thought as the major factor limiting its application to commodity processors. Unlike prior work that deals with memory compression or network compression separately, this paper proposes a unified on-chip distributed data compressor (DISCO), to enable near-zero-latency cache and memory block compression for chip multiprocessors adopting nonuniform cache access. DISCO integrates a multimode cache compressor into the NoC routers and overlaps the de/compression latency with the queuing delay in the network. In addition, cache block evicted to or fetched from the main memory can also be compressed or decompressed during the network queuing time in this unified DISCO compressor. With the support of congestion-awareness, it is shown in the evaluation that DISCO, which unifies the compression solution of the memory hierarchy, dramatically decreases the compression overhead of isolated techniques, and significantly boosts the efficiency of data moving and store.
关键词	Cache chip multiprocessor (CMP) compression memory hierarchy network-on-chip (NoC)
DOI	10.1109/TCAD.2017.2729404
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[61432017] ; National Natural Science Foundation of China[61504153] ; National Natural Science Foundation of China[61532017] ; National Natural Science Foundation of China[61402146] ; National Natural Science Foundation of China[61521092] ; National Key Research and Development Program of China[2016YFF0203500]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:000433091300012
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：4[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/5253
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Wang, Ying; Li, Huawei
作者单位	Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Wang, Ying,Li, Huawei,Han, Yinhe,et al. A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2018,37(6):1265-1277.
APA	Wang, Ying,Li, Huawei,Han, Yinhe,&Li, Xiaowei.(2018).A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,37(6),1265-1277.
MLA	Wang, Ying,et al."A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 37.6(2018):1265-1277.