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Exploring Winograd Convolution for Cost-Effective Neural Network Fault Tolerance 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 卷号: 31, 期号: 11, 页码: 1763-1773
作者:  Xue, Xinghua;  Liu, Cheng;  Liu, Bo;  Huang, Haitong;  Wang, Ying;  Luo, Tao;  Zhang, Lei;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：1/0  |  提交时间：2024/05/20
Fault tolerant systems  Fault tolerance  Artificial neural networks  Convolution  Reliability  Computational modeling  Neurons  Fault-tolerance  soft errors  vulnerability analysis  winograd convolution (WG-Conv)  
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413
作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting
收藏  |  浏览/下载：22/0  |  提交时间：2022/12/07
Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)  
An Edge 3D CNN Accelerator for Low-Power Activity Recognition 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, 卷号: 40, 期号: 5, 页码: 918-930
作者:  Wang, Ying;  Wang, Yongchen;  Shi, Cong;  Cheng, Long;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：36/0  |  提交时间：2021/12/01
Three-dimensional displays  Two dimensional displays  Arrays  Feature extraction  System-on-chip  Redundancy  3D CNN  activity analysis  CNN accelerator  network-on-chip  video  
A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984
作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：66/0  |  提交时间：2019/12/10
Convolutional neural network (CNN)  deep learning  low power  memory subsystem  
Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718
作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：38/0  |  提交时间：2019/12/12
DDR  dynamic random-access memory (DRAM)  memory  refresh  
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：34/0  |  提交时间：2019/12/13
Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)  
OWARE: OPERAND WIDTH AWARE REDUNDANT EXECUTION FOR WHOLE-PROCESSOR ERROR DETECTION 期刊论文
INTELLIGENT AUTOMATION AND SOFT COMPUTING, 2011, 卷号: 17, 期号: 6, 页码: 771-780
作者:  Hu, Yu;  Chen, Zhongliang;  Li, Xiaowei
收藏  |  浏览/下载：67/0  |  提交时间：2019/12/16
narrow-width value  sphere of replication  data-level redundancy  instruction-level redundancy  
Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling 期刊论文
JOURNAL OF SYSTEMS ARCHITECTURE, 2010, 卷号: 56, 期号: 10, 页码: 534-542
作者:  Dong, Jianbo;  Zhang, Lei;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei
收藏  |  浏览/下载：39/0  |  提交时间：2019/12/16
Process variation  Thread-level redundancy  Chip Multiprocessor  Scheduling