An Edge 3D CNN Accelerator for Low-Power Activity Recognition

doi:10.1109/TCAD.2020.3011042

	An Edge 3D CNN Accelerator for Low-Power Activity Recognition
	Wang, Ying 1,2; Wang, Yongchen 1,2; Shi, Cong 3; Cheng, Long 4; Li, Huawei 1,2,5; Li, Xiaowei 1,2
	2021-05-01
发表期刊	IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
ISSN	0278-0070
卷号	40 期号:5 页码:918-930
摘要	3D convolutional neural networks (CNNs) are gaining increasing popularity in the area of video-based action/activity analysis. Compared to 2D convolutions that share the filters in a 2D spatial domain, 3D convolutions further reuse filters in the temporal dimension to capture temporal-domain features in the video. How to exploit the data locality in the temporal dimension directly impacts the energy efficiency of specialized architectures for 3D CNN inference. Prior works on specialized 3D-CNN accelerators employ additional on-chip memories and multicluster architecture to reuse data among the process element (PE) arrays, which is very expensive for low-power chip implementation. Instead of harvesting in-memory data locality, we propose the architecture of systolic cube to exploit the spatial and temporal localities in 3D CNNs, which moves the reusable data in-between PEs connected via a 3D-cube network-on-chip. Furthermore, due to the existence of visual feature reappearance in the temporal domain, there exists a considerable portion of repetitive pixels and activations among the feature maps captured at adjacent time slots. To eliminate such temporal redundancy in 3D CNNs, the proposed accelerator architecture is equipped with a redundancy detection and elimination mechanism, capable of skipping the computations with the same activations and parameters when reusing the convolutional filters along the temporal dimension. In our evaluation, the experimental results show that the systolic-cube architecture contributes to a considerable energy-efficiency boost for state-of-the-art activity-recognition benchmarks and datasets.
关键词	Three-dimensional displays Two dimensional displays Arrays Feature extraction System-on-chip Redundancy 3D CNN activity analysis CNN accelerator network-on-chip video
DOI	10.1109/TCAD.2020.3011042
收录类别	SCI
语种	英语
资助项目	National Natural Science Foundation of China[61874124] ; National Natural Science Foundation of China[61876173] ; Youth Innovation Promotion Association, CAS[2018138] ; National Key Research and Development Program of China[2018AAA0102700]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Computer Science, Interdisciplinary Applications ; Engineering, Electrical & Electronic
WOS记录号	WOS:000641964100009
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：15[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/17792
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Li, Huawei; Li, Xiaowei
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100049, Peoples R China 3.Chongqing Univ, Sch Microelect & Commun Engn, Chongqing 400044, Peoples R China 4.Dublin City Univ, Insight Ctr Data Analyt, Sch Comp, Dublin D09 FW22 9, Ireland 5.Peng Cheng Lab, Shenzhen, Peoples R China
推荐引用方式 GB/T 7714	Wang, Ying,Wang, Yongchen,Shi, Cong,et al. An Edge 3D CNN Accelerator for Low-Power Activity Recognition[J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,2021,40(5):918-930.
APA	Wang, Ying,Wang, Yongchen,Shi, Cong,Cheng, Long,Li, Huawei,&Li, Xiaowei.(2021).An Edge 3D CNN Accelerator for Low-Power Activity Recognition.IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS,40(5),918-930.
MLA	Wang, Ying,et al."An Edge 3D CNN Accelerator for Low-Power Activity Recognition".IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 40.5(2021):918-930.