中国科学院计算技术研究所机构知识库

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限定条件	作者：Li, Huawei    第一作者

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	On-Line Fault Protection for ReRAM-Based Neural Networks 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2023, 卷号: 72, 期号: 2, 页码: 423-437 作者:  Li, Wen;  Wang, Ying;  Liu, Cheng;  He, Yintao;  Liu, Lian;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：12/0  |  提交时间：2023/07/12 Training  Fault detection  Computational modeling  Image edge detection  Memristors  Neural networks  Kernel  Deep neural network  hard fault  ReRAM  reliability  soft fault
	A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4524-4536 作者:  Cui, Aijiao;  Li, Mengyang;  Qu, Gang;  Li, Huawei 收藏  |  浏览/下载：28/0  |  提交时间：2021/12/01 Ciphers  Encryption  Integrated circuits  Side-channel attacks  Testing  Cryptographic hash function  obfuscation logic  scan design  scan-based side-channel attack
	Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 3, 页码: 714-727 作者:  Zhang, Ying;  Chakrabarty, Krishnendu;  Peng, Zebo;  Rezine, Ahmed;  Li, Huawei;  Eles, Petru;  Jiang, Jianhui 收藏  |  浏览/下载：49/0  |  提交时间：2020/12/10 Circuit faults  Built-in self-test  Out of order  Model checking  Integrated circuit modeling  Bounded model checking (BMC)  online testing  out-of-order superscalar processors  software-based self-testing (SBST)
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh
	Path Delay Test Generation Toward Activation of Worst Case Coupling Effects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 11, 页码: 1969-1982 作者:  Zhang, Minjin;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：72/0  |  提交时间：2019/12/16 Crosstalk-induced delay  delay testing  path delay fault  signal integrity  test generation  timing analysis
	Testable Critical Path Selection Considering Process Variation 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, 卷号: E93D, 期号: 1, 页码: 59-67 作者:  Fu, Xiang;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/16 testable critical path selection  process variation
	Compression/scan co-design for reducing test data volume, scan-in power dissipation, and test application time 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2006, 卷号: E89D, 期号: 10, 页码: 2616-2625 作者:  Hu, Yu;  Han, Yinhe;  Li, Xiaowei;  Li, Huawei;  Wen, Xiaoqing 收藏  |  浏览/下载：44/0  |  提交时间：2019/12/16 compression  run-length coding  random access scan  power dissipation  test application time