中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择WOS被引频次升序WOS被引频次降序提交时间升序提交时间降序期刊影响因子升序期刊影响因子降序题名升序题名降序作者升序作者降序发表日期升序发表日期降序
	An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 页码: 12 作者:  Cao, Yuan;  Wu, Yanze;  Wang, Wen;  Lu, Xu;  Chen, Shuai;  Ye, Jing;  Chang, Chip-Hong 收藏  |  浏览/下载：26/0  |  提交时间：2022/06/21 Hardware  Random access memory  Software algorithms  Quantum computing  Field programmable gate arrays  Computers  NIST  Post-quantum cryptography  eXtended Merkle signature scheme  hardware accelerator
	Field-Free 3T2SOT MRAM for Non-Volatile Cache Memories 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 卷号: 67, 期号: 12, 页码: 4660-4669 作者:  Wu, Bi;  Wang, Chao;  Wang, Zhaohao;  Wang, Ying;  Zhang, Deming;  Liu, Dijun;  Zhang, Youguang;  Hu, Xiaobo Sharon 收藏  |  浏览/下载：39/0  |  提交时间：2021/12/01 Random access memory  Magnetic tunneling  Switches  Reliability  Tunneling magnetoresistance  Metals  Transistors  SOT-MRAM  low power  high speed  high reliability
	Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2020, 卷号: 67, 期号: 1, 页码: 108-120 作者:  Wu, Bi;  Dai, Pengcheng;  Wang, Zhaohao;  Wang, Chao;  Wang, Ying;  Yang, Jianlei;  Cheng, Yuanqing;  Liu, Dijun;  Zhang, Youguang;  Zhao, Weisheng;  Hu, Xiaobo Sharon 收藏  |  浏览/下载：51/0  |  提交时间：2020/12/10 NAND-SPIN  spin orbit torque (SOT) MRAM  last level cache  write throughput  high performance
	Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 卷号: 66, 期号: 5, 页码: 1780-1793 作者:  Chen, Xiaoming;  Ni, Kai;  Niemier, Michael T.;  Han, Yinhe;  Datta, Suman;  Hu, Xiaobo Sharon 收藏  |  浏览/下载：85/0  |  提交时间：2019/08/16 Ferroelectric field-effect transistor (FeFET)  field-programmable gate array (FPGA)  lookup table (LUT)  routing switch
	Sinusoidal Clock Sampling for Multigigahertz ADCs 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2011, 卷号: 58, 期号: 12, 页码: 2808-2815 作者:  Bai, Rui;  Wang, Jingguang;  Xia, Lingli;  Zhang, Feng;  Yang, Zongren;  Hu, Weiwu;  Chiang, Patrick 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/16 Flash ADC  jitter  SFDR  sinusoidal clock