Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs

doi:10.1109/TCSI.2018.2874880

	Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs
	Chen, Xiaoming 1; Ni, Kai 2; Niemier, Michael T.3; Han, Yinhe 1; Datta, Suman 2; Hu, Xiaobo Sharon 3
	2019-05-01
发表期刊	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN	1549-8328
卷号	66 期号:5 页码:1780-1793
摘要	As an emerging nonvolatile device, ferroelectric field-effect transistors (FeFETs) have the potential to reduce the power and area by integrating nonvolatile storage elements with logic. The hysteretic behavior allows an FeFET to function as both a nonvolatile storage element and a switch. This paper exploits this feature of FeFETs to design lookup tables (LUTs) and routing switches, which have obvious utility in field-programmable gate arrays (FPGAs). Read and write schemes are also designed for the proposed LUTs and routing switches. Evaluation results based on a calibrated FeFET model show that the proposed designs are competitive in power and performance. For example, compared with conventional complementary metal-oxide-semiconductor (CMOS)-based equivalents, the proposed FeFET-based LUTs and routing elements improve the power-delay product (PDP) by 5.8-16x, respectively, while compared with resistive random-access memory (RRAM)-based equivalents, the proposed designs improve the PDP by 1.14-1.8x. The area of an FeFET-based FPGA is 8% smaller than a conventional CMOS-based FPGA.
关键词	Ferroelectric field-effect transistor (FeFET) field-programmable gate array (FPGA) lookup table (LUT) routing switch
DOI	10.1109/TCSI.2018.2874880
收录类别	SCI
语种	英语
资助项目	Innovative Project of Institute of Computing Technology, CAS[5120186140] ; Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory[61428060401162806001] ; National Science Foundation[1640081] ; Nanoelectronics Research Corporation (NERC)[2698.004]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000465305700012
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：22[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/4262
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Chen, Xiaoming
作者单位	1.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 2.Univ Notre Dame, Dept Elect Engn, Notre Dame, IN 46556 USA 3.Univ Notre Dame, Dept Comp Sci & Engn, Notre Dame, IN 46556 USA
推荐引用方式 GB/T 7714	Chen, Xiaoming,Ni, Kai,Niemier, Michael T.,et al. Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2019,66(5):1780-1793.
APA	Chen, Xiaoming,Ni, Kai,Niemier, Michael T.,Han, Yinhe,Datta, Suman,&Hu, Xiaobo Sharon.(2019).Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,66(5),1780-1793.
MLA	Chen, Xiaoming,et al."Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 66.5(2019):1780-1793.