An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme

doi:10.1109/TCSI.2021.3115786

	An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme
	Cao, Yuan 1,2; Wu, Yanze 1,2; Wang, Wen 3; Lu, Xu 1,2; Chen, Shuai 2; Ye, Jing 4,5; Chang, Chip-Hong 6
	2021-10-04
发表期刊	IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
ISSN	1549-8328
页码	12
摘要	This paper presents a full hardware implementation of the eXtended Merkle Signature Scheme (XMSS), a NIST approved and IETF RFC specified post-quantum cryptography (PQC) algorithm. An optimized node traversal is proposed to enable efficient memory utilization without compromising the computational latency of the L-tree and Merkle tree construction, which are two key components used for the compression of the Winternitz One-Time Signature (WOTS) public key in XMSS. The computation of the authentication path during signature generation has also been significantly sped up by our proposed hardware implementation of the Buchmann, Dahmen, and Schneider (BDS) algorithm. Our implementation has completely avoided the use of block random-access memory, which is known to be vulnerable to side-channel attacks. The memory requirement has been highly optimized for implementation with small flip-flop chains and register counters as pointers for fast data access. To the best of our knowledge, this is the first full hardware implementation of all three key generation, signing and verification operations of XMSS. The design has been prototyped and evaluated on a 28 nm FPGA platform to demonstrate its performance improvements over the most efficient software and hardware/software co-design methods reported to date. Specifically, it increases the computational efficiency of the best reported XMSS implementation for key generation and signature generation by about 20% and 50%, respectively. It can also run at 10% higher clock speed than the fastest hardware implementation of signature verification in FPGA with 8% lower hardware resource utilization.
关键词	Hardware Random access memory Software algorithms Quantum computing Field programmable gate arrays Computers NIST Post-quantum cryptography eXtended Merkle signature scheme hardware accelerator
DOI	10.1109/TCSI.2021.3115786
收录类别	SCI
语种	英语
资助项目	Fundamental Research Funds for Natural Science Foundation of Jiangsu Province[BK20191160] ; Open Research of the State Key Laboratory of Computer Architecture[CARCH201901] ; QingLan Project ; Changzhou Science and Technology Program[CJ20200071] ; Changzhou Science and Technology Program[2020029]
WOS研究方向	Engineering
WOS类目	Engineering, Electrical & Electronic
WOS记录号	WOS:000732423800001
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：9[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/18002
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Chang, Chip-Hong
作者单位	1.Hohai Univ, Coll Internet Things Engn, Changzhou 213022, Peoples R China 2.Rock Solid Secur Lab, Changzhou 213000, Peoples R China 3.Yale Univ, Comp Architecture & Secur Lab, New Haven, CT 06511 USA 4.Chinese Acad Sci, Inst Comp Technol, State Key Lab Comp Architecture, Beijing 100190, Peoples R China 5.Univ Chinese Acad Sci, Beijing 100190, Peoples R China 6.Nanyang Technol Univ, Sch Elect & Elect Engn, Singapore 639798, Singapore
推荐引用方式 GB/T 7714	Cao, Yuan,Wu, Yanze,Wang, Wen,et al. An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,2021:12.
APA	Cao, Yuan.,Wu, Yanze.,Wang, Wen.,Lu, Xu.,Chen, Shuai.,...&Chang, Chip-Hong.(2021).An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme.IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS,12.
MLA	Cao, Yuan,et al."An Efficient Full Hardware Implementation of Extended Merkle Signature Scheme".IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2021):12.