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HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413
作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting
收藏  |  浏览/下载：25/0  |  提交时间：2022/12/07
Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)  
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4524-4536
作者:  Cui, Aijiao;  Li, Mengyang;  Qu, Gang;  Li, Huawei
收藏  |  浏览/下载：29/0  |  提交时间：2021/12/01
Ciphers  Encryption  Integrated circuits  Side-channel attacks  Testing  Cryptographic hash function  obfuscation logic  scan design  scan-based side-channel attack  
Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 3, 页码: 714-727
作者:  Zhang, Ying;  Chakrabarty, Krishnendu;  Peng, Zebo;  Rezine, Ahmed;  Li, Huawei;  Eles, Petru;  Jiang, Jianhui
收藏  |  浏览/下载：50/0  |  提交时间：2020/12/10
Circuit faults  Built-in self-test  Out of order  Model checking  Integrated circuit modeling  Bounded model checking (BMC)  online testing  out-of-order superscalar processors  software-based self-testing (SBST)  
BiloKey : A Scalable Bi-Index Locality-Aware In-Memory Key-Value Store 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2019, 卷号: 30, 期号: 7, 页码: 1528-1540
作者:  Ma, Wenlong;  Zhu, Yuqing;  Li, Cheng;  Guo, Mengying;  Bao, Yungang
收藏  |  浏览/下载：80/0  |  提交时间：2019/08/16
In-memory key-value store  multi-core scalability  locality-aware networking  hybrid index  lock-free access  
Scan chain design for shift power reduction in scan-based testing 期刊论文
SCIENCE CHINA-INFORMATION SCIENCES, 2011, 卷号: 54, 期号: 4, 页码: 767-777
作者:  Li Jia;  Hu Yu;  Li XiaoWei
收藏  |  浏览/下载：66/0  |  提交时间：2019/12/16
low power DfT  scan-based testing  test power reduction  scan chain design  
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2011, 卷号: 30, 期号: 3, 页码: 455-463
作者:  Wu, Shianling;  Wang, Laung-Terng;  Wen, Xiaoqing;  Jiang, Zhigang;  Tan, Lang;  Zhang, Yu;  Hu, Yu;  Jone, Wen-Ben;  Hsiao, Michael S.;  Li, James Chien-Mo;  Huang, Jiun-Lang;  Yu, Lizhen
收藏  |  浏览/下载：68/0  |  提交时间：2019/12/16
Aligned launch-on-capture  at-speed scan testing  double-capture  hybrid launch-on-capture  launch-on-capture  one-hot launch-on-capture  staggered launch-on-capture  
Design for Testability Features of Godson-3 Multicore Microprocessor 期刊论文
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2011, 卷号: 26, 期号: 2, 页码: 302-313
作者:  Qi, Zi-Chu;  Liu, Hui;  Li, Xiang-Ku;  Hu, Wei-Wu
收藏  |  浏览/下载：65/0  |  提交时间：2019/12/16
DFT (design for testability)  TAM (test access mechanism)  multicore processor  low power test  
A Novel Post-Silicon Debug Mechanism Based on Suspect Window 期刊论文
IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, 卷号: E93D, 期号: 5, 页码: 1175-1185
作者:  Jianliang Gao;  Yinhe Han;  Xiaowei Li
收藏  |  浏览/下载：39/0  |  提交时间：2019/12/16
debug  scan dump  real-time trace  suspect window  
Co-optimization of Dynamic/Static Test Power in Scan Test 期刊论文
CHINESE JOURNAL OF ELECTRONICS, 2009, 卷号: 18, 期号: 1, 页码: 54-58
作者:  Wang Wei;  Han Yinhe;  Li Xiaowei;  Fang Fang
收藏  |  浏览/下载：40/0  |  提交时间：2019/12/16
Co-optimization  Test power  Blocking logic  Minimum leakage vector  
Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor 期刊论文
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2008, 卷号: 23, 期号: 6, 页码: 1037-1046
作者:  Wang, Da;  Hu, Yu;  Li, Hua-Wei;  Li, Xiao-Wei
收藏  |  浏览/下载：41/0  |  提交时间：2019/12/16
microprocessor design-for-testability  test generation  built-in self-test  at-speed testing