中国科学院计算技术研究所机构知识库

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	Path Delay Test Generation Toward Activation of Worst Case Coupling Effects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 11, 页码: 1969-1982 作者:  Zhang, Minjin;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：78/0  |  提交时间：2019/12/16 Crosstalk-induced delay  delay testing  path delay fault  signal integrity  test generation  timing analysis
	Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 10, 页码: 1787-1800 作者:  Zhang, Ying;  Li, Huawei;  Min, Yinghua;  Li, Xiaowei 收藏  |  浏览/下载：75/0  |  提交时间：2019/12/16 Crosstalk  crosstalk tolerance  interconnects  network-on-chip (NOC)
	ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2011, 卷号: 60, 期号: 9, 页码: 1219-1232 作者:  Yan, Guihai;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：69/0  |  提交时间：2019/12/16 Lifetime reliability  self-adaptive  aging sensor  timing adaptation  NBTI
	SVFD: A Versatile Online Fault Detection Scheme via Checking of Stability Violation 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 9, 页码: 1627-1640 作者:  Yan, Guihai;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：72/0  |  提交时间：2019/12/16 Aging  delay fault  online fault detection  soft error  stability violation
	A New Multiple-Round Dimension-Order Routing for Networks-on-Chip 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, 卷号: E94D, 期号: 4, 页码: 809-821 作者:  Fu, Binzhang;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：75/0  |  提交时间：2019/12/16 network-on-chip (NoC)  fault-tolerant routing  multiple round dimension-order routing  turn model
	Scan chain design for shift power reduction in scan-based testing 期刊论文 SCIENCE CHINA-INFORMATION SCIENCES, 2011, 卷号: 54, 期号: 4, 页码: 767-777 作者:  Li Jia;  Hu Yu;  Li XiaoWei 收藏  |  浏览/下载：71/0  |  提交时间：2019/12/16 low power DfT  scan-based testing  test power reduction  scan chain design
	MicroFix: Using Timing Interpolation and Delay Sensors for Power Reduction 期刊论文 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2011, 卷号: 16, 期号: 2, 页码: 21 作者:  Yan, Guihai;  Han, Yinhe;  Liu, Hui;  Liang, Xiaoyao;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/16 Design  Performance  Reliability  Power reduction  fine-grained adaptability  DVFS  timing interpolation  delay sensor
	Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling 期刊论文 JOURNAL OF SYSTEMS ARCHITECTURE, 2010, 卷号: 56, 期号: 10, 页码: 534-542 作者:  Dong, Jianbo;  Zhang, Lei;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei 收藏  |  浏览/下载：50/0  |  提交时间：2019/12/16 Process variation  Thread-level redundancy  Chip Multiprocessor  Scheduling
	Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2010, 卷号: E93D, 期号: 8, 页码: 2223-2232 作者:  Liu, Jun;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：52/0  |  提交时间：2019/12/16 selective encoding  test data compression  test power reduction  flexible grouping  X-filling
	X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2010, 卷号: 18, 期号: 7, 页码: 1081-1092 作者:  Li, Jia;  Xu, Qiang;  Hu, Yu;  Li, Xiaowei 收藏  |  浏览/下载：43/0  |  提交时间：2019/12/16 At-speed scan-based testing  low-power testing  X-filling