中文版 | English

在结果中检索

CSpace

浏览/检索结果: 共10条，第1-10条 帮助

已选(0)清除 条数/页：   排序方式：
Trident: The Acceleration Architecture for High-Performance Private Set Intersection 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 4, 页码: 1152-1167
作者:  Zhang, Jinkai;  Yang, Yinghao;  Zhou, Zhe;  Hu, Zhicheng;  Zhao, Xin;  Chang, Liang;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：5/0  |  提交时间：2025/06/25
Protocols  Receivers  Cryptography  Hardware  Central Processing Unit  Random access memory  Data privacy  Polynomials  Field programmable gate arrays  Computer architecture  Private set intersection (PSI)  fully homomorphic encryption (FHE)  FPGA accelerator  privacy computing  
General Purpose Deep Learning Accelerator Based on Bit Interleaving 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 5, 页码: 1470-1483
作者:  Chang, Liang;  Lu, Hang;  Li, Chenglong;  Zhao, Xin;  Hu, Zhicheng;  Zhou, Jun;  Li, Xiaowei
收藏  |  浏览/下载：27/0  |  提交时间：2024/12/06
Synchronization  Parallel processing  Computational modeling  Training  Pragmatics  Power demand  Hardware acceleration  Accelerator  bit-level sparsity  deep neural network (DNN)  
Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 3, 页码: 878-891
作者:  Li, Hongyan;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：27/0  |  提交时间：2024/05/20
Deep learning accelerator  deep neural network (DNN)  fp8 format  
Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762
作者:  Yang, Yinghao;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：56/0  |  提交时间：2024/05/20
FPGA accelerator  fully homomorphic encryption (FHE)  near data processing (NDP)  privacy computing  
BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 卷号: 31, 期号: 1, 页码: 90-103
作者:  Li, Hongyan;  Lu, Hang;  Wang, Haoxuan;  Deng, Shengji;  Li, Xiaowei
收藏  |  浏览/下载：36/0  |  提交时间：2023/07/12
Deep learning accelerator  deep neural network (DNN)  hardware runtime pruning  
VNet: a versatile network to train real-time semantic segmentation models on a single GPU 期刊论文
SCIENCE CHINA-INFORMATION SCIENCES, 2022, 卷号: 65, 期号: 3, 页码: 2
作者:  Li, Wenxing;  Lin, Ning;  Zhang, Mingzhe;  Lu, Hang;  Chen, Xiaoming;  Li, Xiaowei
收藏  |  浏览/下载：69/0  |  提交时间：2021/12/01
Architecting Effectual Computation for Machine Learning Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：113/0  |  提交时间：2020/12/10
Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits  
ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 8, 页码: 1438-1451
作者:  Lu, Hang;  Chang, Yisong;  Yan, Guihai;  Lin, Ning;  Wei, Xin;  Li, Xiaowei
收藏  |  浏览/下载：99/0  |  提交时间：2019/12/10
Many-core processors  networks-on-chip (NoCs)  power management  shuttle networks-on-chip (ShuttleNoC)  
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 卷号: 23, 期号: 12, 页码: 3053-3064
作者:  Lu, Hang;  Fu, Binzhang;  Wang, Ying;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei
收藏  |  浏览/下载：58/0  |  提交时间：2019/12/13
Cloud processor  networks-on-chip (NoCs)  performance isolation  relaxed isolation (RISO)  workload consolidation  
无权访问的条目 学位论文
作者:  路航
Adobe PDF(7367Kb)  |  收藏  |  浏览/下载：0/0  |  提交时间：2015/07/03