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FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 9, 页码: 2889-2902
作者:  Liu, Rui;  Zhang, Xiaoyu;  Xie, Zhiwen;  Wang, Xinyu;  Li, Zerun;  Chen, Xiaoming;  Han, Yinhe;  Tang, Minghua
收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04
Computing-in-memory (CiM)  cryptographic algorithm  ferroelectric field-effect transistor (FeFET)  instruc-tion set architecture (ISA)  
Scalable and Conflict-Free NTT Hardware Accelerator Design: Methodology, Proof, and Implementation 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 5, 页码: 1504-1517
作者:  Mu, Jianan;  Ren, Yi;  Wang, Wen;  Hu, Yizhong;  Chen, Shuai;  Chang, Chip-Hong;  Fan, Junfeng;  Ye, Jing;  Cao, Yuan;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：9/0  |  提交时间：2023/12/04
Memory access pattern  number theoretic transform (NTT)  post-quantum cryptography (PQC)  scalable hardware design  
Re-FeMAT: A Reconfigurable Multifunctional FeFET-Based Memory Architecture 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 11, 页码: 5071-5084
作者:  Zhang, Xiaoyu;  Liu, Rui;  Song, Tao;  Yang, Yuxin;  Han, Yinhe;  Chen, Xiaoming
收藏  |  浏览/下载：13/0  |  提交时间：2023/07/12
Convolutional neural network (CNN)  ferroelectric field-effect transistor (FeFET)  few-shot learning  in-memory processing  ternary content-addressable memory (TCAM)  
Search-Free Inference Acceleration for Sparse Convolutional Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2156-2169
作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Wu, Jigang;  Chang, Liang;  Liu, Peng;  Xu, Haobo
收藏  |  浏览/下载：24/0  |  提交时间：2022/12/07
Internal interconnection  memory bandwidth  sparse accelerators  sparse convolution neural networks (CNNs)  
A Fast Precision Tuning Solution for Always-On DNN Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 5, 页码: 1236-1248
作者:  Wang, Ying;  He, Yintao;  Cheng, Long;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：25/0  |  提交时间：2022/12/07
Computer architecture  Neural networks  Computational modeling  Approximate computing  Tuning  Switches  Microprocessors  Always-on  CNN  computing-in-memory (CiM)  resistive RAM  
Rubik: A Hierarchical Architecture for Efficient Graph Neural Network Training 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 4, 页码: 936-949
作者:  Chen, Xiaobing;  Wang, Yuke;  Xie, Xinfeng;  Hu, Xing;  Basak, Abanti;  Liang, Ling;  Yan, Mingyu;  Deng, Lei;  Ding, Yufei;  Du, Zidong;  Xie, Yuan
收藏  |  浏览/下载：21/0  |  提交时间：2022/12/07
Deep learning accelerator  graph neural network (GNN)  
An Automated Quantization Framework for High-Utilization RRAM-Based PIM 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 3, 页码: 583-596
作者:  Li, Bing;  Qu, Songyun;  Wang, Ying
收藏  |  浏览/下载：24/0  |  提交时间：2022/12/07
Quantization (signal)  Neural networks  Computational modeling  Data models  Hardware  Resource management  Arrays  AutoML  neural network  processing-in-memory (PIM)  quantization  resistive memory (RRAM)  
Cambricon-G: A Polyvalent Energy-Efficient Accelerator for Dynamic Graph Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 1, 页码: 116-128
作者:  Song, Xinkai;  Zhi, Tian;  Fan, Zhe;  Zhang, Zhenxing;  Zeng, Xi;  Li, Wei;  Hu, Xing;  Du, Zidong;  Guo, Qi;  Chen, Yunji
收藏  |  浏览/下载：29/0  |  提交时间：2022/06/21
Accelerator  architecture  graph neural networks (GNNs)  
An Edge 3D CNN Accelerator for Low-Power Activity Recognition 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, 卷号: 40, 期号: 5, 页码: 918-930
作者:  Wang, Ying;  Wang, Yongchen;  Shi, Cong;  Cheng, Long;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：38/0  |  提交时间：2021/12/01
Three-dimensional displays  Two dimensional displays  Arrays  Feature extraction  System-on-chip  Redundancy  3D CNN  activity analysis  CNN accelerator  network-on-chip  video  
Swallow: A Versatile Accelerator for Sparse Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4881-4893
作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Xu, Haobo
收藏  |  浏览/下载：28/0  |  提交时间：2021/12/01
Accelerator  convolutional (Conv) layers  fully connected (FC) layers  sparse neural networks (SNNs)