中国科学院计算技术研究所机构知识库

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限定条件	作者：Li, Xiaowei    第一作者

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Saving Energy of RRAM-Based Neural Accelerator Through State-Aware Computing 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 7, 页码: 2115-2127 作者:  He, Yintao;  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：27/0  |  提交时间：2022/12/07 Computer architecture  Microprocessors  Resistance  Power demand  Training  Biological neural networks  Optimization  Low power (LP)  neural networks  processing-in-memory  resistive random-access memory (RRAM)
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh
	Power-Utility-Driven Write Management for MLC PCM 期刊论文 ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, 2017, 卷号: 13, 期号: 3, 页码: 22 作者:  Li, Bing;  Hu, Yu;  Wang, Ying;  Ye, Jing;  Li, Xiaowei 收藏  |  浏览/下载：54/0  |  提交时间：2019/12/12 Phase change memory  multi-level  main memory  power  write management  optimization
	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13 3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput
	Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 1, 页码: 92-102 作者:  Han, Yinhe;  Dong, Jianbo;  Weng, Kaiheng;  Wang, Ying;  Li, Xiaowei 收藏  |  浏览/下载：42/0  |  提交时间：2019/12/13 Endurance  phase-change random access memory (PRAM)  wear leveling (WL)
	Compression/scan co-design for reducing test data volume, scan-in power dissipation, and test application time 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2006, 卷号: E89D, 期号: 10, 页码: 2616-2625 作者:  Hu, Yu;  Han, Yinhe;  Li, Xiaowei;  Li, Huawei;  Wen, Xiaoqing 收藏  |  浏览/下载：45/0  |  提交时间：2019/12/16 compression  run-length coding  random access scan  power dissipation  test application time