Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation

doi:10.1109/TVLSI.2015.2395415

	Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation
	Han, Yinhe 1; Dong, Jianbo ; Weng, Kaiheng ; Wang, Ying ; Li, Xiaowei
	2016
发表期刊	IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
ISSN	1063-8210
卷号	24 期号:1 页码:92-102
摘要	The limited write endurance is one of the major obstacles for phase-change random access memory (PRAM)-based main memory. Traditionally, wear-leveling (WL) techniques were proposed to enhance its lifetime by balancing write traffic. However, these techniques do not concern the endurance variation in PRAM chips. When different PRAM cells have distinct endurance, balanced writes results in lifetime degradation due to the weakest cells. In this paper, we first define a new metric-wear rate (i.e., writes/endurance) considering both the write traffic and endurance distribution from application and hardware, respectively. After investigating the writing behavior of applications and endurance variation, we propose an architecture-level leveling mechanism to balance wear rate of cells across the PRAM chip. Hardware and algorithm to support the proposed leveling mechanism are presented. Moreover, there is an important tradeoff between endurance improvement and swapping data volume. To co-optimize endurance and swapping, this situation is formulated as a maximum weight perfect matching problem in bipartite graph. Thereafter, a novel algorithm that minimizes wear-rate and swapping by employing Kuhn-Munkras algorithm is proposed to maximize PRAM lifetime and minimize performance degradation. The experimental results show similar to 17x lifetime improvement over prior WL.
关键词	Endurance phase-change random access memory (PRAM) wear leveling (WL)
DOI	10.1109/TVLSI.2015.2395415
收录类别	SCI
语种	英语
资助项目	National Basic Research Program of China (973)[2011CB302503] ; National Natural Science Foundation of China[61100016] ; National Natural Science Foundation of China[61376043] ; National Natural Science Foundation of China[61221062] ; National Natural Science Foundation of China[61402439]
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:000367261900009
出版者	IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
引用统计	被引频次：12[WOS] [WOS记录] [WOS相关记录]
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/9000
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Han, Yinhe
作者单位	1.Chinese Acad Sci, State Key Lab Comp Architecture, Inst Comp Technol, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Han, Yinhe,Dong, Jianbo,Weng, Kaiheng,et al. Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,2016,24(1):92-102.
APA	Han, Yinhe,Dong, Jianbo,Weng, Kaiheng,Wang, Ying,&Li, Xiaowei.(2016).Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation.IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS,24(1),92-102.
MLA	Han, Yinhe,et al."Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation".IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 24.1(2016):92-102.