中国科学院计算技术研究所机构知识库

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限定条件	作者：Li, Xiaowei    第一作者

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 3, 页码: 878-891 作者:  Li, Hongyan;  Lu, Hang;  Li, Xiaowei 收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20 Deep learning accelerator  deep neural network (DNN)  fp8 format
	HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413 作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting 收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07 Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)
	An Edge 3D CNN Accelerator for Low-Power Activity Recognition 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2021, 卷号: 40, 期号: 5, 页码: 918-930 作者:  Wang, Ying;  Wang, Yongchen;  Shi, Cong;  Cheng, Long;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：37/0  |  提交时间：2021/12/01 Three-dimensional displays  Two dimensional displays  Arrays  Feature extraction  System-on-chip  Redundancy  3D CNN  activity analysis  CNN accelerator  network-on-chip  video
	Architecting Effectual Computation for Machine Learning Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667 作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：88/0  |  提交时间：2020/12/10 Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits
	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984 作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：68/0  |  提交时间：2019/12/10 Convolutional neural network (CNN)  deep learning  low power  memory subsystem