中国科学院计算技术研究所机构知识库

浏览/检索结果: 共7条，第1-7条

帮助

限定条件	作者：Li, Xiaowei    第一作者    资助项目：National Natural Science Foundation of China[61521092]

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	BZIP: A compact data memory system for UTXO-based blockchains 期刊论文 JOURNAL OF SYSTEMS ARCHITECTURE, 2020, 卷号: 109, 页码: 8 作者:  Jiang, Shuhao;  Li, Jiajun;  Gong, Shijun;  Yan, Junchao;  Yan, Guihai;  Sun, Yi;  Li, Xiaowei 收藏  |  浏览/下载：49/0  |  提交时间：2020/12/10 UTXO  Blockchain  Data Compression  IoT
	SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2019, 卷号: 68, 期号: 11, 页码: 1663-1677 作者:  Li, Jiajun;  Jiang, Shuhao;  Gong, Shijun;  Wu, Jingya;  Yan, Junchao;  Yan, Guihai;  Li, Xiaowei 收藏  |  浏览/下载：41/0  |  提交时间：2020/12/10 Convolutional neural networks  accelerator architecture  hardware acceleration
	SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks 期刊论文 ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2019, 卷号: 24, 期号: 1, 页码: 27 作者:  Li, Jiajun;  Yan, Guihai;  Lu, Wenyan;  Gong, Shijun;  Jiang, Shuhao;  Wu, Jingya;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/04/03 Deep neural networks  convolutional neural networks  accelerator  architecture  resource utilization  complementary effect
	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984 作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：68/0  |  提交时间：2019/12/10 Convolutional neural network (CNN)  deep learning  low power  memory subsystem
	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277 作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：67/0  |  提交时间：2019/12/10 Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh
	STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296 作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/12 Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)