中国科学院计算技术研究所机构知识库

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限定条件	作者：Han, Yinhe    第一作者

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Fault Modeling and Efficient Testing of Memristor-Based Memory 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2021, 卷号: 68, 期号: 11, 页码: 4444-4455 作者:  Liu, Peng;  You, Zhiqiang;  Wu, Jigang;  Liu, Bosheng;  Han, Yinhe;  Chakrabarty, Krishnendu 收藏  |  浏览/下载：25/0  |  提交时间：2022/06/21 Electrical defects  fault model  defect-oriented testing  March algorithm  non-volatile memory
	Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs 期刊论文 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 卷号: 66, 期号: 5, 页码: 1780-1793 作者:  Chen, Xiaoming;  Ni, Kai;  Niemier, Michael T.;  Han, Yinhe;  Datta, Suman;  Hu, Xiaobo Sharon 收藏  |  浏览/下载：83/0  |  提交时间：2019/08/16 Ferroelectric field-effect transistor (FeFET)  field-programmable gate array (FPGA)  lookup table (LUT)  routing switch
	moDNN: Memory Optimal Deep Neural Network Training on Graphics Processing Units 期刊论文 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2019, 卷号: 30, 期号: 3, 页码: 646-661 作者:  Chen, Xiaoming;  Chen, Danny Ziyi;  Han, Yinhe;  Hu, Xiaobo Sharon 收藏  |  浏览/下载：303/0  |  提交时间：2019/04/03 Deep neural networks  graphics processing units  memory usage
	PIMSim: A Flexible and Detailed Processing-in-Memory Simulator 期刊论文 IEEE COMPUTER ARCHITECTURE LETTERS, 2019, 卷号: 18, 期号: 1, 页码: 6-9 作者:  Xu, Sheng;  Chen, Xiaoming;  Wang, Ying;  Han, Yinhe;  Qian, Xuehai;  Li, Xiaowei 收藏  |  浏览/下载：80/0  |  提交时间：2019/04/03 Processing-in-memory  simulator  heterogeneous computing  memory system
	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277 作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：67/0  |  提交时间：2019/12/10 Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)
	STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296 作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/12 Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)