中国科学院计算技术研究所机构知识库

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限定条件	作者：Han, Yinhe    第一作者    作者：Li, Xiaowei    资助项目：National Basic Research Program of China (973)[2011CB302503]

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	EcoUp: Towards Economical Datacenter Upgrading 期刊论文 IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2016, 卷号: 27, 期号: 7, 页码: 1968-1981 作者:  Yan, Guihai;  Ma, Jun;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：61/0  |  提交时间：2019/12/13 Datacenter upgrading  cost efficiency  performance prediction  recommender systems  collaborative filtering
	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13 3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput
	An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2016, 卷号: 65, 期号: 2, 页码: 367-381 作者:  Ma, Jun;  Yan, Guihai;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：36/0  |  提交时间：2019/12/13 Heterogeneous manycores  scale-out  scale-up  analytical model  power efficiency  runtime management
	Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 1, 页码: 92-102 作者:  Han, Yinhe;  Dong, Jianbo;  Weng, Kaiheng;  Wang, Ying;  Li, Xiaowei 收藏  |  浏览/下载：42/0  |  提交时间：2019/12/13 Endurance  phase-change random access memory (PRAM)  wear leveling (WL)
	A signal degradation reduction method for memristor ratioed logic (MRL) gates 期刊论文 IEICE ELECTRONICS EXPRESS, 2015, 卷号: 12, 期号: 8, 页码: 6 作者:  Liu, Bosheng l;  Wang, Ying;  You, Zhiqiang;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/13 full adder  memristor ratioed logic (MRL) gate
	ReviveNet: A Self-Adaptive Architecture for Improving Lifetime Reliability via Localized Timing Adaptation 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2011, 卷号: 60, 期号: 9, 页码: 1219-1232 作者:  Yan, Guihai;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：64/0  |  提交时间：2019/12/16 Lifetime reliability  self-adaptive  aging sensor  timing adaptation  NBTI
	Statistical lifetime reliability optimization considering joint effect of process variation and aging 期刊论文 INTEGRATION-THE VLSI JOURNAL, 2011, 卷号: 44, 期号: 3, 页码: 185-191 作者:  Jin, Song;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：67/0  |  提交时间：2019/12/16 Lifetime reliability  Process variation  NBTI  Duty cycle  Gate sizing
	A New Multiple-Round Dimension-Order Routing for Networks-on-Chip 期刊论文 IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2011, 卷号: E94D, 期号: 4, 页码: 809-821 作者:  Fu, Binzhang;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：70/0  |  提交时间：2019/12/16 network-on-chip (NoC)  fault-tolerant routing  multiple round dimension-order routing  turn model
	Performance-asymmetry-aware scheduling for Chip Multiprocessors with static core coupling 期刊论文 JOURNAL OF SYSTEMS ARCHITECTURE, 2010, 卷号: 56, 期号: 10, 页码: 534-542 作者:  Dong, Jianbo;  Zhang, Lei;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei 收藏  |  浏览/下载：40/0  |  提交时间：2019/12/16 Process variation  Thread-level redundancy  Chip Multiprocessor  Scheduling