中国科学院计算技术研究所机构知识库

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限定条件	出处：IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 卷号: 29, 期号: 3, 页码: 472-484 作者:  Xu, Dawen;  Zhu, Ziyang;  Liu, Cheng;  Wang, Ying;  Zhao, Shuang;  Zhang, Lei;  Liang, Huaguo;  Li, Huawei;  Cheng, Kwang-Ting 收藏  |  浏览/下载：38/0  |  提交时间：2021/12/01 Neural networks  Circuit faults  Hardware  Acceleration  Reliability  Analytical models  Computational modeling  Integrated circuit reliability  reliability
	LMDet: A "Naturalness" Statistical Method for Hardware Trojan Detection 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2018, 卷号: 26, 期号: 4, 页码: 720-732 作者:  Shen, Haihua;  Tan, Huazhe;  Li, Huawei;  Zhang, Feng;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/10 Hardware Trojan (HT) detection  natural language processing (NLP)  n-gram language model  statistical analysis
	A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586 作者:  Chen, Shuai;  Li, Hao;  Chiang, Patrick Yin 收藏  |  浏览/下载：38/0  |  提交时间：2019/12/13 All-digital clock and data recovery (ADCDR)  delay-locked loop (DLL)  forwarded-clock (FC) receiver  high-density interconnect  jitter tolerance  multicore processor  process variation  voltage and temperature drift