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Taming Process Variations in CNFET for Efficient Last-Level Cache Design 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 卷号: 30, 期号: 4, 页码: 418-431
作者:  Xu, Dawen;  Feng, Zhuangyu;  Liu, Cheng;  Li, Li;  Wang, Ying;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07
CNTFETs  Delays  Transistors  Layout  Very large scale integration  Radio frequency  Energy consumption  nanotube field-effect transistor (CNFET)  last-level cache (LLC)  process variation (PV)  variation-aware cache  
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 卷号: 27, 期号: 8, 页码: 1851-1860
作者:  Wu, Bi;  Zhang, Beibei;  Cheng, Yuanqing;  Wang, Ying;  Liu, Dijun;  Zhao, Weisheng
收藏  |  浏览/下载：77/0  |  提交时间：2019/12/10
Error correction code (ECC)  last level cache (LLC)  reliability  spin-transfer-torque magnetoresistive random-access memory (STT-MRAM)  temperature  
Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2019, 卷号: 27, 期号: 1, 页码: 159-172
作者:  Yin, Xunzhao;  Chen, Xiaoming;  Niemier, Michael;  Hu, Xiaobo Sharon
收藏  |  浏览/下载：81/0  |  提交时间：2019/04/03
Ferroelectric FET (FeFET)  logic-in-memory (LiM)  nonvolatile (NV) memory  
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586
作者:  Chen, Shuai;  Li, Hao;  Chiang, Patrick Yin
收藏  |  浏览/下载：38/0  |  提交时间：2019/12/13
All-digital clock and data recovery (ADCDR)  delay-locked loop (DLL)  forwarded-clock (FC) receiver  high-density interconnect  jitter tolerance  multicore processor  process variation  voltage and temperature drift