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ApproxDup: Developing an Approximate Instruction Duplication Mechanism for Efficient SDC Detection in GPGPUs 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 4, 页码: 1051-1064
作者:  Wei, Xiaohui;  Jiang, Nan;  Yue, Hengshan;  Wang, Xiaonan;  Zhao, Jianpeng;  Li, Guangli;  Qiu, Meikang
收藏  |  浏览/下载：3/0  |  提交时间：2024/05/20
Instruction sets  Reliability  Resilience  Circuit faults  Registers  Kernel  Graphics processing units  Approximate computing  GPGPUs  instruction duplication  silent data corruptions (SDCs)  soft error  
Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762
作者:  Yang, Yinghao;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：6/0  |  提交时间：2024/05/20
FPGA accelerator  fully homomorphic encryption (FHE)  near data processing (NDP)  privacy computing  
SpecWands: An Efficient Priority-Based Scheduler Against Speculation Contention Attacks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4477-4490
作者:  Tang, Bowen;  Wu, Chenggang;  Yew, Pen-Chung;  Zhang, Yinqian;  Xie, Mengyao;  Lai, Yuanming;  Kang, Yan;  Wang, Wei;  Wei, Qiang;  Wang, Zhe
收藏  |  浏览/下载：8/0  |  提交时间：2024/05/20
Resource contention  scheduling strategy  simultaneous multithreading (SMT)  transient execution attack (TEA)  
Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 11, 页码: 3993-4003
作者:  Chen, Weiwei;  Wang, Ying;  Xu, Ying;  Gao, Chengsi;  Han, Yinhe;  Zhang, Lei
收藏  |  浏览/下载：14/0  |  提交时间：2023/07/12
Resource management  Predictive models  Runtime  Generators  Generative adversarial networks  Computational modeling  Training  Design space exploration  generative adversarial network (GAN)  reconfigurable processor  
An Automated Quantization Framework for High-Utilization RRAM-Based PIM 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 3, 页码: 583-596
作者:  Li, Bing;  Qu, Songyun;  Wang, Ying
收藏  |  浏览/下载：24/0  |  提交时间：2022/12/07
Quantization (signal)  Neural networks  Computational modeling  Data models  Hardware  Resource management  Arrays  AutoML  neural network  processing-in-memory (PIM)  quantization  resistive memory (RRAM)  
Swallow: A Versatile Accelerator for Sparse Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4881-4893
作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Xu, Haobo
收藏  |  浏览/下载：28/0  |  提交时间：2021/12/01
Accelerator  convolutional (Conv) layers  fully connected (FC) layers  sparse neural networks (SNNs)  
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4524-4536
作者:  Cui, Aijiao;  Li, Mengyang;  Qu, Gang;  Li, Huawei
收藏  |  浏览/下载：29/0  |  提交时间：2021/12/01
Ciphers  Encryption  Integrated circuits  Side-channel attacks  Testing  Cryptographic hash function  obfuscation logic  scan design  scan-based side-channel attack  
Fusion-Catalyzed Pruning for Optimizing Deep Learning on Intelligent Edge Devices 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 11, 页码: 3614-3626
作者:  Li, Guangli;  Ma, Xiu;  Wang, Xueying;  Liu, Lei;  Xue, Jingling;  Feng, Xiaobing
收藏  |  浏览/下载：48/0  |  提交时间：2021/12/01
Deep learning system  edge intelligence  model compression and acceleration  neural networks  
Leveraging the Error Resilience of Neural Networks for Designing Highly Energy Efficient Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2015, 卷号: 34, 期号: 8, 页码: 1223-1235
作者:  Du, Zidong;  Lingamneni, Avinash;  Chen, Yunji;  Palem, Krishna V.;  Temam, Olivier;  Wu, Chengyong
收藏  |  浏览/下载：54/0  |  提交时间：2019/12/13
Accelerator architectures  energy efficient  hardware neuron network  inexact computing