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EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2021, 卷号: 70, 期号: 9, 页码: 1511-1525
作者:  Liang, Shengwen;  Wang, Ying;  Liu, Cheng;  He, Lei;  Li, Huawei;  Xu, Dawen;  Li, Xiaowei
收藏  |  浏览/下载：40/0  |  提交时间：2021/12/01
Neural networks  Hardware  System-on-chip  Task analysis  Feature extraction  Memory management  Graph neural network  accelerator architecture  hardware acceleration  
SynergyFlow: An Elastic Accelerator Architecture Supporting Batch Processing of Large-Scale Deep Neural Networks 期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2019, 卷号: 24, 期号: 1, 页码: 27
作者:  Li, Jiajun;  Yan, Guihai;  Lu, Wenyan;  Gong, Shijun;  Jiang, Shuhao;  Wu, Jingya;  Li, Xiaowei
收藏  |  浏览/下载：71/0  |  提交时间：2019/04/03
Deep neural networks  convolutional neural networks  accelerator  architecture  resource utilization  complementary effect  
Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748
作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：54/0  |  提交时间：2019/12/12
Deep learning  error tolerance  neural network (NN)  timing variation  
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296
作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：71/0  |  提交时间：2019/12/12
Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)  
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：54/0  |  提交时间：2019/12/13
3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput  
RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 卷号: 23, 期号: 12, 页码: 3053-3064
作者:  Lu, Hang;  Fu, Binzhang;  Wang, Ying;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei
收藏  |  浏览/下载：40/0  |  提交时间：2019/12/13
Cloud processor  networks-on-chip (NoCs)  performance isolation  relaxed isolation (RISO)  workload consolidation  
Data Remapping for Static NUCA in Degradable Chip Multiprocessors 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 卷号: 23, 期号: 5, 页码: 879-892
作者:  Wang, Ying;  Zhang, Lei;  Han, Yin-He;  Li, Hua-Wei;  Li, Xiaowei
收藏  |  浏览/下载：38/0  |  提交时间：2019/12/13
Chip multiprocessor (CMP)  fault tolerant  network-on-chip (NoC)  nonuniform cache architecture (NUCA)  
Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2011, 卷号: 19, 期号: 10, 页码: 1787-1800
作者:  Zhang, Ying;  Li, Huawei;  Min, Yinghua;  Li, Xiaowei
收藏  |  浏览/下载：64/0  |  提交时间：2019/12/16
Crosstalk  crosstalk tolerance  interconnects  network-on-chip (NOC)  
Embedded test decompressor to reduce the required channels and vector memory of tester for complex processor circuit 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2007, 卷号: 15, 期号: 5, 页码: 531-540
作者:  Han, Yinhe;  Hu, Yu;  Li, Xiaowei;  Li, Huawei;  Chandra, Anshuman
收藏  |  浏览/下载：39/0  |  提交时间：2019/12/16
automatic test equipment (ATE)  Godson processor  MUX network  test stimulus decompression