中国科学院计算技术研究所机构知识库

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限定条件	作者：Lu, Hang分Lu, Hang

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Mortar-FP8: Morphing the Existing FP32 Infrastructure for High-Performance Deep Learning Acceleration 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2024, 卷号: 43, 期号: 3, 页码: 878-891 作者:  Li, Hongyan;  Lu, Hang;  Li, Xiaowei 收藏  |  浏览/下载：2/0  |  提交时间：2024/05/20 Deep learning accelerator  deep neural network (DNN)  fp8 format
	Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762 作者:  Yang, Yinghao;  Lu, Hang;  Li, Xiaowei 收藏  |  浏览/下载：6/0  |  提交时间：2024/05/20 FPGA accelerator  fully homomorphic encryption (FHE)  near data processing (NDP)  privacy computing
	BitXpro: Regularity-Aware Hardware Runtime Pruning for Deep Neural Networks 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2023, 卷号: 31, 期号: 1, 页码: 90-103 作者:  Li, Hongyan;  Lu, Hang;  Wang, Haoxuan;  Deng, Shengji;  Li, Xiaowei 收藏  |  浏览/下载：13/0  |  提交时间：2023/07/12 Deep learning accelerator  deep neural network (DNN)  hardware runtime pruning
	VNet: a versatile network to train real-time semantic segmentation models on a single GPU 期刊论文 SCIENCE CHINA-INFORMATION SCIENCES, 2022, 卷号: 65, 期号: 3, 页码: 2 作者:  Li, Wenxing;  Lin, Ning;  Zhang, Mingzhe;  Lu, Hang;  Chen, Xiaoming;  Li, Xiaowei 收藏  |  浏览/下载：44/0  |  提交时间：2021/12/01
	Architecting Effectual Computation for Machine Learning Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667 作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：88/0  |  提交时间：2020/12/10 Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits
	ShuttleNoC: Power-Adaptable Communication Infrastructure for Many-Core Processors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 8, 页码: 1438-1451 作者:  Lu, Hang;  Chang, Yisong;  Yan, Guihai;  Lin, Ning;  Wei, Xin;  Li, Xiaowei 收藏  |  浏览/下载：75/0  |  提交时间：2019/12/10 Many-core processors  networks-on-chip (NoCs)  power management  shuttle networks-on-chip (ShuttleNoC)
	RISO: Enforce Noninterfered Performance With Relaxed Network-on-Chip Isolation in Many-Core Cloud Processors 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2015, 卷号: 23, 期号: 12, 页码: 3053-3064 作者:  Lu, Hang;  Fu, Binzhang;  Wang, Ying;  Han, Yinhe;  Yan, Guihai;  Li, Xiaowei 收藏  |  浏览/下载：39/0  |  提交时间：2019/12/13 Cloud processor  networks-on-chip (NoCs)  performance isolation  relaxed isolation (RISO)  workload consolidation