中国科学院计算技术研究所机构知识库

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限定条件	作者：Wang, Ying    第一作者    发表日期：2022

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	Dadu-SV: Accelerate Stereo Vision Processing on NPU 期刊论文 IEEE EMBEDDED SYSTEMS LETTERS, 2022, 卷号: 14, 期号: 4, 页码: 191-194 作者:  Min, Feng;  Wang, Ying;  Xu, Haobo;  Huang, Junpei;  Wang, Yujie;  Zou, Xingqi;  Lu, Meixuan;  Han, Yinhe 收藏  |  浏览/下载：14/0  |  提交时间：2023/07/12 Hardware acceleration  neural computing  neural processing unit (NPU)  semiglobal matching (SGM)  stereo vision
	Amphis: Managing Reconfigurable Processor Architectures With Generative Adversarial Learning 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 11, 页码: 3993-4003 作者:  Chen, Weiwei;  Wang, Ying;  Xu, Ying;  Gao, Chengsi;  Han, Yinhe;  Zhang, Lei 收藏  |  浏览/下载：14/0  |  提交时间：2023/07/12 Resource management  Predictive models  Runtime  Generators  Generative adversarial networks  Computational modeling  Training  Design space exploration  generative adversarial network (GAN)  reconfigurable processor
	HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413 作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting 收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07 Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)
	Taming Process Variations in CNFET for Efficient Last-Level Cache Design 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2022, 卷号: 30, 期号: 4, 页码: 418-431 作者:  Xu, Dawen;  Feng, Zhuangyu;  Liu, Cheng;  Li, Li;  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：26/0  |  提交时间：2022/12/07 CNTFETs  Delays  Transistors  Layout  Very large scale integration  Radio frequency  Energy consumption  nanotube field-effect transistor (CNFET)  last-level cache (LLC)  process variation (PV)  variation-aware cache
	LINAC: A Spatially Linear Accelerator for Convolutional Neural Networks 期刊论文 IEEE COMPUTER ARCHITECTURE LETTERS, 2022, 卷号: 21, 期号: 1, 页码: 29-32 作者:  Xiao, Hang;  Xu, Haobo;  Wang, Ying;  Wang, Yujie;  Han, Yinhe 收藏  |  浏览/下载：21/0  |  提交时间：2022/12/07 Linear particle accelerator  Correlation  Kernel  Convolution  Linear regression  System-on-chip  Quantization (signal)  Neural network  acceleration  convolution  linear regression  bit-sparsity