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Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators 期刊论文
IEEE DESIGN & TEST, 2024, 卷号: 41, 期号: 5, 页码: 46-54
作者:  Liu, Rui;  Li, Zerun;  Zhang, Xiaoyu;  Li, Wanqian;  Shen, Libo;  Tang, Rui;  Luo, Zhejian;  Chen, Xiaoming;  Han, Yinhe;  Tang, Minghua
收藏  |  浏览/下载：1/0  |  提交时间：2024/12/06
Computer architecture  Cryptography  Optimization  Table lookup  Hardware acceleration  Resource management  Space exploration  Computing-in-memory  electronic design automation  cryptographic algorithm  automatic generation  
MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 11, 页码: 4112-4125
作者:  Zhu, Zhenhua;  Sun, Hanbo;  Xie, Tongxin;  Zhu, Yu;  Dai, Guohao;  Xia, Lixue;  Niu, Dimin;  Chen, Xiaoming;  Hu, Xiaobo Sharon;  Cao, Yu;  Xie, Yuan;  Yang, Huazhong;  Wang, Yu
收藏  |  浏览/下载：9/0  |  提交时间：2024/05/20
Computational modeling  Computer architecture  Integrated circuit modeling  Scheduling  Hardware  Memristors  Convolutional neural networks  Hardware modeling tool  processing-in-memory (PIM)  software-hardware co-optimization  
A Framework for Neural Network Architecture and Compile Co-optimization 期刊论文
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS, 2023, 卷号: 22, 期号: 1, 页码: 24
作者:  Chen, Weiwei;  Wang, Ying;  Xu, Ying;  Gao, Chengsi;  Liu, Cheng;  Zhang, Lei
收藏  |  浏览/下载：21/0  |  提交时间：2023/07/12
DNN-scheduling Co-design  hardware-aware neural architecture search  compiler optimization  
HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2022, 卷号: 41, 期号: 10, 页码: 3400-3413
作者:  Liu, Cheng;  Chu, Cheng;  Xu, Dawen;  Wang, Ying;  Wang, Qianlong;  Li, Huawei;  Li, Xiaowei;  Cheng, Kwang-Ting
收藏  |  浏览/下载：37/0  |  提交时间：2022/12/07
Circuit faults  Computational modeling  Deep learning  Hardware  Redundancy  Neural networks  Computer architecture  Deep learning accelerator (DLA)  fault detection  fault tolerance  hybrid computing architecture (HyCA)  
EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2021, 卷号: 70, 期号: 9, 页码: 1511-1525
作者:  Liang, Shengwen;  Wang, Ying;  Liu, Cheng;  He, Lei;  Li, Huawei;  Xu, Dawen;  Li, Xiaowei
收藏  |  浏览/下载：47/0  |  提交时间：2021/12/01
Neural networks  Hardware  System-on-chip  Task analysis  Feature extraction  Memory management  Graph neural network  accelerator architecture  hardware acceleration  
Hardware Acceleration for GCNs via Bidirectional Fusion 期刊论文
IEEE COMPUTER ARCHITECTURE LETTERS, 2021, 卷号: 20, 期号: 1, 页码: 4
作者:  Li, Han;  Yan, Mingyu;  Yang, Xiaocheng;  Deng, Lei;  Li, Wenming;  Ye, Xiaochun;  Fan, Dongrui;  Xie, Yuan
收藏  |  浏览/下载：44/0  |  提交时间：2021/12/01
Random access memory  Computational modeling  Analytical models  Hardware  Engines  Computer architecture  Transforms  Graph convolutional neural networks  hardware accelerator  bidirectional execution  inter-phase fusion  
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4791-4804
作者:  Lan, Yazhu;  Nixon, Kent W.;  Guo, Qingli;  Zhang, Guohe;  Xu, Yuanchao;  Li, Hai;  Chen, Yiran
收藏  |  浏览/下载：49/0  |  提交时间：2021/12/01
Perturbation methods  Computational modeling  Data integrity  Detectors  Optimization  Field programmable gate arrays  Hardware  Adversarial attacks  confidence detection  deep neural networks (DNNs)  FPGA-based hardware architecture  sensor pattern noise (SPN)  
Accelerating DNN-based 3D point cloud processing for mobile computing 期刊论文
SCIENCE CHINA-INFORMATION SCIENCES, 2019, 卷号: 62, 期号: 11, 页码: 11
作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Li, Jiajun;  Xu, Haobo;  Li, Xiaowei
收藏  |  浏览/下载：234/0  |  提交时间：2019/12/10
deep neural network acceleration  point cloud data  neighbor point search  mobile robotics  hardware architecture  
SqueezeFlow: A Sparse CNN Accelerator Exploiting Concise Convolution Rules 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2019, 卷号: 68, 期号: 11, 页码: 1663-1677
作者:  Li, Jiajun;  Jiang, Shuhao;  Gong, Shijun;  Wu, Jingya;  Yan, Junchao;  Yan, Guihai;  Li, Xiaowei
收藏  |  浏览/下载：48/0  |  提交时间：2020/12/10
Convolutional neural networks  accelerator architecture  hardware acceleration  
Ecosystem of Things: Hardware, Software, and Architecture 期刊论文
PROCEEDINGS OF THE IEEE, 2019, 卷号: 107, 期号: 8, 页码: 1563-1583
作者:  Chao, Lu;  Peng, Xiaohui;  Xu, Zhiwei;  Zhang, Lei
收藏  |  浏览/下载：45/0  |  提交时间：2020/12/10
Architecture  ecosystem of things (EoT)  edge computing  hardware  Internet of Things (IoT)  software