中文版 | English

在结果中检索

CSpace

浏览/检索结果: 共24条，第1-10条 帮助

已选(0)清除 条数/页：   排序方式：
Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 2, 页码: 603-616
作者:  Du, Yibo;  Wang, Ying;  Wang, Mengdi;  Li, Xiaowei;  Han, Yinhe
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Hardware  Chiplets  Homomorphic encryption  Polynomials  Vectors  Scheduling algorithms  Noise  Program processors  Design automation  Computational efficiency  Chiplet  fully homomorphic encryption (FHE)  hardware-software co-design  heterogeneous architecture  
Computational Burst Buffers: Accelerating HPC I/O via In-Storage Compression Offloading 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2026, 卷号: 37, 期号: 2, 页码: 518-532
作者:  Chen, Xiang;  Lu, Bing;  Long, Haoquan;  Luo, Huizhang;  Ma, Yili;  Tan, Guangming;  Tao, Dingwen;  Wu, Fei;  Lu, Tao
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Hardware  Computer architecture  File systems  Nonvolatile memory  Bandwidth  Engines  Prototypes  Data compression  Software  Flash memories  high performance computing  solid state drives  
An Efficient Paillier Homomorphic Encryption Circuit With Optional CRT Acceleration for IoT 期刊论文
IEEE INTERNET OF THINGS JOURNAL, 2025, 卷号: 12, 期号: 22, 页码: 48146-48158
作者:  Feng, Jundong;  Zhang, Xiaoliang;  Zilic, Zeljko;  Hao, Qinfen;  Wang, Junchao
收藏  |  浏览/下载：3/0  |  提交时间：2026/05/25
Hardware  Internet of Things  Homomorphic encryption  Computational efficiency  Computer architecture  Software  Parallel processing  Optimization  Costs  Circuit synthesis  Chinese remainder theorem (CRT)  circuit  homomorphic encryption  Internet of Things (IoT)  paillier  
In-Situ NAS: A Plug-and-Search Neural Architecture Search Framework Across Hardware Platforms 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 9, 页码: 2856-2869
作者:  Lv, Hao;  Zhang, Lei;  Wang, Ying
收藏  |  浏览/下载：21/0  |  提交时间：2025/12/03
Neural architecture search  deep learning  optimization  hardware-aware  AutoML  performance evaluation  Neural architecture search  deep learning  optimization  hardware-aware  AutoML  performance evaluation  
Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3409-3422
作者:  Long, Boyu;  Han, Yinhe;  Sun, Xian-He;  Chen, Xiaoming
收藏  |  浏览/下载：22/0  |  提交时间：2025/12/03
Logic  Computer architecture  Integrated circuit interconnections  Hardware  Routing  Circuits  Table lookup  Decoding  Performance evaluation  Logic gates  Processing in memory  resistive random-access memory (RRAM)  software-hardware co-design  ternary content-addressable memory (TCAM)  
KPU: Kernel Processing Unit for in-Memory Analytical Query Processing 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 8, 页码: 2702-2716
作者:  Wu, Jingya;  Lu, Wenyan;  Fan, Haishuang;  Kong, Hao;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：27/0  |  提交时间：2025/12/03
Kernel  Bandwidth  Hardware  Central Processing Unit  Query processing  Programming  Parallel processing  Computers  Satellites  Database  domain-specific computer architecture  programmability  SQL  SQL  
Efficient Hardware Architecture Design of K-Means Clustering Algorithm for AV1 Palette Mode Coding 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2025, 卷号: 72, 期号: 8, 页码: 1078-1082
作者:  Huang, Xiaofeng;  Lin, Jiaqing;  Liu, Fengguang;  Ji, Wen;  Yin, Haibing;  Ma, Siwei
收藏  |  浏览/下载：18/0  |  提交时间：2025/12/03
Random access memory  Hardware  Engines  Indexes  Encoding  Bandwidth  Clustering algorithms  Heuristic algorithms  Throughput  Memory management  K-means clustering  Palette mode  Alliance for Open Media Video 1 (AV1)  data reuse  hardware architecture  
CODA: A Computation-Driven Paradigm for Sparse DNN Acceleration 期刊论文
IEEE COMPUTER ARCHITECTURE LETTERS, 2025, 卷号: 24, 期号: 2, 页码: 381-384
作者:  Liu, Yanhuan;  Li, Wenming;  Zhang, Kunming;  Liu, Tianyu;  Ye, Xiaochun;  An, Xuejun
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Software  Hardware  Computational modeling  Sparse matrices  Pipelines  Indexes  Data models  Spatial databases  Computational efficiency  Vectors  Computation-driven architecture  sparse DNN acceleration  dataflow paradigm  unstructured sparsity  work tokenizer  dynamic execution core  asynchronous execution  
DFU-E: A Dataflow Architecture for Edge DSP and AI Applications 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2025, 卷号: 36, 期号: 6, 页码: 1100-1114
作者:  Li, Wenming;  Fan, Zhihua;  Liu, Tianyu;  Wang, Zhen;  Wu, Haibin;  Wu, Meng;  Zhang, Kunming;  Liu, Yanhuan;  Sun, Ninghui;  Ye, Xiaochun;  Fan, Dongrui
收藏  |  浏览/下载：68/0  |  提交时间：2025/06/25
Artificial intelligence  Hardware  Edge computing  Computer architecture  Computational modeling  Single instruction multiple data  Energy efficiency  Target recognition  Radar polarimetry  Real-time systems  Dataflow architecture  edge computing  digital signal processing  AI  multi-layer dataflow mechanism  
Trident: The Acceleration Architecture for High-Performance Private Set Intersection 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 4, 页码: 1152-1167
作者:  Zhang, Jinkai;  Yang, Yinghao;  Zhou, Zhe;  Hu, Zhicheng;  Zhao, Xin;  Chang, Liang;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：61/0  |  提交时间：2025/06/25
Protocols  Receivers  Cryptography  Hardware  Central Processing Unit  Random access memory  Data privacy  Polynomials  Field programmable gate arrays  Computer architecture  Private set intersection (PSI)  fully homomorphic encryption (FHE)  FPGA accelerator  privacy computing