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In-Memory Wallace Tree Multipliers Based on Majority Gates Within Voltage-Gated SOT-MRAM Crossbar Arrays 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2024, 页码: 8
作者:  Hui, Yajuan;  Li, Qingzhen;  Wang, Leimin;  Liu, Cheng;  Zhang, Deming;  Miao, Xiangshui
收藏  |  浏览/下载:21/0  |  提交时间:2024/05/20
In-memory computing  majority gates  voltage-gated SOT-MRAM  Wallace tree multiplier  
A simplified architecture for modulo (2(n)+1) multiplication 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 1998, 卷号: 47, 期号: 3, 页码: 333-337
作者:  Ma, YT
收藏  |  浏览/下载:75/0  |  提交时间:2019/12/16
convolution  Fermat number transform  RNS arithmetic  modulo (2(n)+1) multiplication  Booth's algorithm  Wallace tree  carry save adder  CSA array  carry lookahead adder