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A 16-Gb/s 3-tap adaptive DFE in 12-nm FinFET CMOS technology 期刊论文
MICROELECTRONICS JOURNAL, 2024, 卷号: 149, 页码: 10
作者:  Sun, Xinzhuo;  Ding, Jianping;  Yang, Liqiong;  Lin, Changlong;  Li, Yao;  Zhao, Yiqiang
收藏  |  浏览/下载:1/0  |  提交时间:2024/12/06
Decision feedback equalizers (DFEs)  Adaptive equalization  Regenerating sampler (RG-Sampler)  Sign-sign least-mean-squares (SSLMS)  2-D eye-opening monitor (EOM)  Receiver  
A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 2, 页码: 578-586
作者:  Chen, Shuai;  Li, Hao;  Chiang, Patrick Yin
收藏  |  浏览/下载:46/0  |  提交时间:2019/12/13
All-digital clock and data recovery (ADCDR)  delay-locked loop (DLL)  forwarded-clock (FC) receiver  high-density interconnect  jitter tolerance  multicore processor  process variation  voltage and temperature drift