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GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3816-3829
作者:  Fan, Haishuang;  Meng, Rui;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Field programmable gate arrays  Redundancy  Indexes  Graphics processing units  Central Processing Unit  Integrated circuit modeling  Computational modeling  Engines  Design automation  Data models  Accelerator  FPGA  Graph processing  
Co-ViSu: Accelerating Video Super-Resolution With Codec Information Reuse 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3451-3464
作者:  Fan, Haishuang;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai
收藏  |  浏览/下载：4/0  |  提交时间：2025/12/03
Binary sequences  Streaming media  Decoding  Artificial neural networks  Superresolution  Kernel  Engines  Design automation  Video codecs  Throughput  Accelerator  codec  FPGA  super-resolution (SR)  
HEAT: Efficient Vision Transformer Accelerator With Hybrid-Precision Quantization 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2025, 卷号: 72, 期号: 5, 页码: 758-762
作者:  Zhao, Pan;  Xue, Donghui;  Wu, Licheng;  Chang, Liang;  Tan, Haining;  Han, Yinhe;  Zhou, Jun
收藏  |  浏览/下载：16/0  |  提交时间：2025/06/25
Vision transformer  accelerator  hybrid-precision quantization  FPGA  Vision transformer  accelerator  hybrid-precision quantization  FPGA  
Trident: The Acceleration Architecture for High-Performance Private Set Intersection 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 4, 页码: 1152-1167
作者:  Zhang, Jinkai;  Yang, Yinghao;  Zhou, Zhe;  Hu, Zhicheng;  Zhao, Xin;  Chang, Liang;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：38/0  |  提交时间：2025/06/25
Protocols  Receivers  Cryptography  Hardware  Central Processing Unit  Random access memory  Data privacy  Polynomials  Field programmable gate arrays  Computer architecture  Private set intersection (PSI)  fully homomorphic encryption (FHE)  FPGA accelerator  privacy computing  
ADS-CNN: Adaptive Dataflow Scheduling for lightweight CNN accelerator on FPGAs 期刊论文
FUTURE GENERATION COMPUTER SYSTEMS-THE INTERNATIONAL JOURNAL OF ESCIENCE, 2024, 卷号: 158, 页码: 138-149
作者:  Wan, Yi;  Xie, Xianzhong;  Chen, Junfan;  Xie, Kunpeng;  Yi, Dezhi;  Lu, Ye;  Gai, Keke
收藏  |  浏览/下载：33/0  |  提交时间：2024/12/06
Lightweight convolutional neural networks  FPGA  Accelerator  Adaptive dataflow  Unified computing engine  Tiling strategy  
Poseidon-NDP: Practical Fully Homomorphic Encryption Accelerator Based on Near Data Processing Architecture 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 12, 页码: 4749-4762
作者:  Yang, Yinghao;  Lu, Hang;  Li, Xiaowei
收藏  |  浏览/下载：91/0  |  提交时间：2024/05/20
FPGA accelerator  fully homomorphic encryption (FHE)  near data processing (NDP)  privacy computing  
AKGF: Automatic Kernel Generation for DNN on CPU-FPGA 期刊论文
COMPUTER JOURNAL, 2023, 页码: 9
作者:  Dong, Dong;  Jiang, Hongxu;  Diao, Boyu
收藏  |  浏览/下载：46/0  |  提交时间：2023/12/04
DNN accelerated compilers  polyhedral model  heterogeneous computing  CPU-FPGA  
Improving Seed-Based FPGA Packing with Indirect Connection for Realization of Neural Networks 期刊论文
ELECTRONICS, 2023, 卷号: 12, 期号: 12, 页码: 13
作者:  Yu, Le;  Guo, Baojin;  Zhi, Tian;  Bai, Lida
收藏  |  浏览/下载：39/0  |  提交时间：2023/12/04
FPGA  EDA  packing  seed-based  indirect connections  
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 12, 页码: 4791-4804
作者:  Lan, Yazhu;  Nixon, Kent W.;  Guo, Qingli;  Zhang, Guohe;  Xu, Yuanchao;  Li, Hai;  Chen, Yiran
收藏  |  浏览/下载：101/0  |  提交时间：2021/12/01
Perturbation methods  Computational modeling  Data integrity  Detectors  Optimization  Field programmable gate arrays  Hardware  Adversarial attacks  confidence detection  deep neural networks (DNNs)  FPGA-based hardware architecture  sensor pattern noise (SPN)  
Power and Area Efficient FPGA Building Blocks Based on Ferroelectric FETs 期刊论文
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2019, 卷号: 66, 期号: 5, 页码: 1780-1793
作者:  Chen, Xiaoming;  Ni, Kai;  Niemier, Michael T.;  Han, Yinhe;  Datta, Suman;  Hu, Xiaobo Sharon
收藏  |  浏览/下载：132/0  |  提交时间：2019/08/16
Ferroelectric field-effect transistor (FeFET)  field-programmable gate array (FPGA)  lookup table (LUT)  routing switch