中国科学院计算技术研究所机构知识库

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	Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 2, 页码: 603-616 作者:  Du, Yibo;  Wang, Ying;  Wang, Mengdi;  Li, Xiaowei;  Han, Yinhe 收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25 Hardware  Chiplets  Homomorphic encryption  Polynomials  Vectors  Scheduling algorithms  Noise  Program processors  Design automation  Computational efficiency  Chiplet  fully homomorphic encryption (FHE)  hardware-software co-design  heterogeneous architecture
	Systematic Methodology of Modeling and Design Space Exploration for CMOS Image Sensors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 2, 页码: 1047-1060 作者:  Ma, Tianrui;  Gao, Zhe;  Chen, Zhe;  Kakarala, Ramakrishna;  Shan, Charles;  Cao, Weidong;  Zhang, Xuan 收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25 CMOS image sensors (CIS)  design space explo ration (DSE)  integrated circuit modeling  integrated circuit modeling
	JPnR: A Length-Matching Placement and Routing Framework for Single-Flux-Quantum Circuits 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2026, 卷号: 75, 期号: 1, 页码: 290-304 作者:  Fu, Rongliang;  Zhou, Minglei;  Chen, Siyan;  Chen, Xinda;  Huang, Junying;  Ye, Xiaochun;  Zhang, Zhimin;  Ho, Tsung-Yi 收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25 Logic gates  Routing  Circuits  Clocks  Physical design  Delays  Logic  Trees (botanical)  Switches  Layout  Superconducting electronics  single-flux-quantum  placement  routing  length-matching  clock-aware
	DFGAS: Exploring the Balance of HW-SW Scheduling through the DFG-Aware Scheme 期刊论文 ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2025, 卷号: 22, 期号: 4, 页码: 26 作者:  Liu, Tianyu;  Fan, Zhihua;  Li, Wenming;  Wang, Zhen;  Qiu, Yuhang;  Tang, Shengzhong;  Wu, Haibin;  Liu, Yanhuan;  Ye, Xiaochun;  Fan, Dongrui 收藏  |  浏览/下载：3/0  |  提交时间：2026/05/25 CGRA  hardware-software co-design  network-on-chip
	Compressing and Accelerating Sparse CNNs Using Sign-Reserved Toeplitz Filters and Input Activation Density-aware Dataflow 期刊论文 ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2025, 卷号: 22, 期号: 4, 页码: 23 作者:  Wang, Zhen;  Liu, Tianyu;  Fan, Zhihua;  Li, Wenming;  Qiu, Yuhang;  Zhang, Zhiyuan;  An, Xuejun;  Fan, Dongrui;  Ye, Xiaochun 收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25 Convolutional neural networks  accelerators  sparsity  algorithm-hardware co-design
	Toward Comprehensive Design Space Exploration on Heterogeneous Multi-core Processors 期刊论文 ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2025, 卷号: 22, 期号: 4, 页码: 27 作者:  Wang, Duo;  Yan, Mingyu;  Han, Dengke;  Ye, Xiaochun;  Fan, Dongrui 收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25 Design space exploration  heterogeneous multi-core processors  prediction model  CPU microarchitecture  resource management
	Joint Beamforming and Transmission Design for Hybrid Backscatter-HTT Communication System 期刊论文 IEEE INTERNET OF THINGS JOURNAL, 2025, 卷号: 12, 期号: 21, 页码: 45437-45452 作者:  Du, Chenyang;  Guo, Jing;  Wang, Xinyi;  Yu, Hanxiao;  Fei, Zesong;  Zhou, Xiangyun;  Durrani, Salman 收藏  |  浏览/下载：26/0  |  提交时间：2025/12/03 Backscatter communication  energy harvesting  harvest-then-transmit (HTT)  harvest-then-transmit (HTT)  multiple antennas  multiple antennas  transmission design  transmission design  transmission design
	CollFree: Exploiting Full-Duplex Capabilities in WiFi Contention for Enhanced Throughput Efficiency 期刊论文 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 2025, 卷号: 43, 期号: 11, 页码: 3875-3888 作者:  Zhao, Qinglin;  Xu, Fangxin;  Feng, Li;  Zhou, MengChu;  Shen, Meng;  Zhang, Peiyun;  Sun, Yi 收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25 Wireless fidelity  Protocols  Throughput  Data communication  Time-domain analysis  Electronic mail  Sensors  Charge coupled devices  Analytical models  Uplink  Wireless full-duplex  slot  clear channel assessment  contention mechanism  protocol design
	OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine-Learning Tasks in Logic Synthesis 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3830-3843 作者:  Ni, Liwei;  Wang, Rui;  Liu, Miao;  Meng, Xingyu;  Lin, Xiaoze;  Liu, Junfeng;  Luo, Guojie;  Chu, Zhufei;  Qian, Weikang;  Yang, Xiaoyan;  Xie, Biwei;  Li, Xingquan;  Li, Huawei 收藏  |  浏览/下载：29/0  |  提交时间：2025/12/03 Logic  Logic gates  Delays  Optimization  Machine learning  Hardware design languages  Boolean functions  Computer science  Benchmark testing  Wire  Adaptive  application  dataset  logic synthesis  machine learning (ML)
	GRACE: An End-to-End Graph Processing Accelerator on FPGA With Graph Reordering Engine 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 10, 页码: 3816-3829 作者:  Fan, Haishuang;  Meng, Rui;  Sun, Qichu;  Wu, Jingya;  Lu, Wenyan;  Li, Xiaowei;  Yan, Guihai 收藏  |  浏览/下载：20/0  |  提交时间：2025/12/03 Field programmable gate arrays  Redundancy  Indexes  Graphics processing units  Central Processing Unit  Integrated circuit modeling  Computational modeling  Engines  Design automation  Data models  Accelerator  FPGA  Graph processing