中国科学院计算技术研究所机构知识库

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	A QoS-QoR Aware CNN Accelerator Design Approach 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2019, 卷号: 38, 期号: 11, 页码: 1995-2007 作者:  Wang, Ying;  Li, Huawei;  Cheng, Long;  Li, Xiaowei 收藏  |  浏览/下载：56/0  |  提交时间：2020/12/10 Approximate computing  convolutional neural network (CNN)  deep learning (DL)  quality of service (QoS)  real-time
	A Case of On-Chip Memory Subsystem Design for Low-Power CNN Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 10, 页码: 1971-1984 作者:  Wang, Ying;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：76/0  |  提交时间：2019/12/10 Convolutional neural network (CNN)  deep learning  low power  memory subsystem
	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277 作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：75/0  |  提交时间：2019/12/10 Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)
	Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 10, 页码: 2736-2748 作者:  Wang, Ying;  Deng, Jiachao;  Fang, Yuntan;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：60/0  |  提交时间：2019/12/12 Deep learning  error tolerance  neural network (NN)  timing variation
	Retention-Aware DRAM Assembly and Repair for Future FGR Memories 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2017, 卷号: 36, 期号: 5, 页码: 705-718 作者:  Wang, Ying;  Han, Yin-He;  Wang, Cheng;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：44/0  |  提交时间：2019/12/12 DDR  dynamic random-access memory (DRAM)  memory  refresh