中国科学院计算技术研究所机构知识库

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	A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 4, 页码: 1109-1122 作者:  Li, Zerun;  Chen, Xiaoming;  Yang, Yuxin;  Min, Feng;  Zhang, Xiaoyu;  Han, Yinhe 收藏  |  浏览/下载：6/0  |  提交时间：2025/06/25 Bandwidth  Memory management  Computational modeling  System-on-chip  Software  Hardware  Computer architecture  Three-dimensional displays  Performance evaluation  Data communication  Large-scale graph processing  near memory computing  memory system  accelerator
	Crypto-DSEDA: A Domain-Specific EDA Flow for CiM-Based Cryptographic Accelerators 期刊论文 IEEE DESIGN & TEST, 2024, 卷号: 41, 期号: 5, 页码: 46-54 作者:  Liu, Rui;  Li, Zerun;  Zhang, Xiaoyu;  Li, Wanqian;  Shen, Libo;  Tang, Rui;  Luo, Zhejian;  Chen, Xiaoming;  Han, Yinhe;  Tang, Minghua 收藏  |  浏览/下载：12/0  |  提交时间：2024/12/06 Computer architecture  Cryptography  Optimization  Table lookup  Hardware acceleration  Resource management  Space exploration  Computing-in-memory  electronic design automation  cryptographic algorithm  automatic generation
	GAS: General-Purpose In-Memory-Computing Accelerator for Sparse Matrix Multiplication 期刊论文 IEEE TRANSACTIONS ON COMPUTERS, 2024, 卷号: 73, 期号: 6, 页码: 1427-1441 作者:  Zhang, Xiaoyu;  Li, Zerun;  Liu, Rui;  Chen, Xiaoming;  Han, Yinhe 收藏  |  浏览/下载：19/0  |  提交时间：2024/12/06 Sparse matrices  FeFETs  Computer architecture  Arrays  Nonvolatile memory  Microprocessors  Vectors  Sparse matrix multiplication  in-memory computing  SpMV  SpMSpV  SpMM  SpMSpM
	FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2023, 卷号: 42, 期号: 9, 页码: 2889-2902 作者:  Liu, Rui;  Zhang, Xiaoyu;  Xie, Zhiwen;  Wang, Xinyu;  Li, Zerun;  Chen, Xiaoming;  Han, Yinhe;  Tang, Minghua 收藏  |  浏览/下载：37/0  |  提交时间：2023/12/04 Computing-in-memory (CiM)  cryptographic algorithm  ferroelectric field-effect transistor (FeFET)  instruc-tion set architecture (ISA)