A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing

doi:10.1109/TC.2024.3514292

	A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing
	Li, Zerun 1,2; Chen, Xiaoming 1,2; Yang, Yuxin 1,2; Min, Feng 1,2; Zhang, Xiaoyu 1,2; Han, Yinhe 1,2
	2025-04-01
发表期刊	IEEE TRANSACTIONS ON COMPUTERS
ISSN	0018-9340
卷号	74 期号:4 页码:1109-1122
摘要	Graph processing plays an important role in many practical applications. However, the inherent characteristics of graph processing, including random memory access and the low computation-to-communication ratio, make it difficult to efficiently execute on traditional computing architectures, such as CPUs and GPUs. Near-memory computing has the characteristics of low latency and high bandwidth. It is widely regarded as a promising direction for designing graph processing accelerators. However, the storage space of a single device cannot meet the demand of large-scale graph processing. Using multiple devices will bring lots of inter-device data transmission, which may counteract the benefits of near-memory computing. To fundamentally reduce the data transmission overhead, we propose a data-centric graph processing framework for systems with multiple near-memory computing devices. The framework uses a data-centric programming model as the software hardware interface. For software, we propose an optimized data flow and a heuristic multi-step weighted maximum matching algorithm to achieve efficient inter-device communication and ensure load balancing. For hardware, we design a data reuse driven task controller and a data type-aware on-chip memory, which can effectively improve the utilization of the on-chip memory. Compared with the two most recent near-memory graph accelerators, our framework significantly reduces energy consumption and inter-device communication.
关键词	Bandwidth Memory management Computational modeling System-on-chip Software Hardware Computer architecture Three-dimensional displays Performance evaluation Data communication Large-scale graph processing near memory computing memory system accelerator
DOI	10.1109/TC.2024.3514292
收录类别	SCI
语种	英语
WOS研究方向	Computer Science ; Engineering
WOS类目	Computer Science, Hardware & Architecture ; Engineering, Electrical & Electronic
WOS记录号	WOS:001442951900012
出版者	IEEE COMPUTER SOC
引用统计
文献类型	期刊论文
条目标识符	http://119.78.100.204/handle/2XEOYT63/40689
专题	中国科学院计算技术研究所期刊论文_英文
通讯作者	Chen, Xiaoming; Han, Yinhe
作者单位	1.Chinese Acad Sci, Inst Comp Technol, Beijing 100190, Peoples R China 2.Univ Chinese Acad Sci, Beijing 100190, Peoples R China
推荐引用方式 GB/T 7714	Li, Zerun,Chen, Xiaoming,Yang, Yuxin,et al. A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing[J]. IEEE TRANSACTIONS ON COMPUTERS,2025,74(4):1109-1122.
APA	Li, Zerun,Chen, Xiaoming,Yang, Yuxin,Min, Feng,Zhang, Xiaoyu,&Han, Yinhe.(2025).A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing.IEEE TRANSACTIONS ON COMPUTERS,74(4),1109-1122.
MLA	Li, Zerun,et al."A Data-Centric Software-Hardware Co-Designed Architecture for Large-Scale Graph Processing".IEEE TRANSACTIONS ON COMPUTERS 74.4(2025):1109-1122.