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SuperEncoder: Towards Efficient Neural Approximate Quantum State Preparation 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2026, 卷号: 75, 期号: 3, 页码: 916-927
作者:  Zhao, Yilun;  Wang, Bingmeng;  Jiang, Wenle;  Pan, Xiwei;  Li, Bing;  Han, Yinhe;  Wang, Ying
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Quantum state  Qubit  Training  Runtime  Optimization  Encoding  Iterative methods  Vectors  Quantum circuit  Quantum algorithm  Quantum state preparation  performance optimization  
Chiplever: A Hardware-Software Co-Design Framework Toward Extension of Chiplet System for Fully Homomorphic Encryption 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2026, 卷号: 45, 期号: 2, 页码: 603-616
作者:  Du, Yibo;  Wang, Ying;  Wang, Mengdi;  Li, Xiaowei;  Han, Yinhe
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
Hardware  Chiplets  Homomorphic encryption  Polynomials  Vectors  Scheduling algorithms  Noise  Program processors  Design automation  Computational efficiency  Chiplet  fully homomorphic encryption (FHE)  hardware-software co-design  heterogeneous architecture  
Online detection of hardware Trojan enabled packet tampering attack on network-on-chip: A Bayesian approach 期刊论文
INTEGRATION-THE VLSI JOURNAL, 2026, 卷号: 106, 页码: 15
作者:  Wang, Xiaohang;  Cao, Ge;  Zhao, Yiming;  Jiang, Yingtao;  Singh, Amit Kumar;  Yang, Mei;  Wang, Liang;  Han, Yinhe;  Guo, Fen
收藏  |  浏览/下载：22/0  |  提交时间：2025/12/03
Networks-on-chip  Online detection of hardware Trojan  
Dadu-E: Rethinking the Role of Large Language Model in Robotic Computing Pipelines 期刊论文
JOURNAL OF FIELD ROBOTICS, 2025, 页码: 24
作者:  Sun, Wenhao;  Hou, Sai;  Wang, Zixuan;  Yu, Bo;  Liu, Shaoshan;  Yang, Xu;  Liang, Shuai;  Gan, Yiming;  Han, Yinhe
收藏  |  浏览/下载：1/0  |  提交时间：2026/05/25
closed-loop planning  large language models  memory augmentation  robotic planning  
ScaleGS: Closing the Gap between Real-time 3D Gaussian Splatting and Real-time XR Rendering 期刊论文
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 2025, 卷号: 22, 期号: 4, 页码: 26
作者:  Chang, Kaiyan;  Gan, Yiming;  Zhu, Wenlong;  Wang, Kun;  Chen, Zhirong;  Cheng, Yuan;  Han, Yinhe;  Li, Huawei;  Wang, Ying
收藏  |  浏览/下载：2/0  |  提交时间：2026/05/25
VR/AR  accelerator  hardware  
A data-centric chip design agent framework for Verilog code generation 期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2025, 卷号: 30, 期号: 6, 页码: 27
作者:  Chang, Kaiyan;  Zhu, Wenlong;  Wang, Kun;  He, Xinyang;  Yang, Nan;  Chen, Zhirong;  Jin, Dantong;  Li, Cangyuan;  Zhou, Yunhao;  Yan, Hao;  Zhao, Zhuoliang;  Cheng, Yuan;  Wang, Mengdi;  Liang, Shengwen;  Han, Yinhe;  Li, Xiaowei;  Li, Huawei;  Wang, Ying
收藏  |  浏览/下载：2/0  |  提交时间：2026/05/25
Large language model  hardware generation  data augmentation  
AutoSilicon: Scaling Up RTL Design Generation Capability of Large Language Models 期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2025, 卷号: 30, 期号: 6, 页码: 21
作者:  Li, Cangyuan;  Chen, Chujie;  Pan, Yudong;  Xu, Wenjun;  Liu, Yiqi;  Chang, Kaiyan;  Wang, Yujie;  Wang, Mengdi;  Li, Huawei;  Han, Yinhe;  Wang, Ying
收藏  |  浏览/下载：2/0  |  提交时间：2026/05/25
Verilog code generation  LLM  agent  verilog  
Re-Meltrix: A Reconfigurable Processing-in-Memory Architecture Based on RRAM and Function Synthesis 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2025, 卷号: 44, 期号: 9, 页码: 3409-3422
作者:  Long, Boyu;  Han, Yinhe;  Sun, Xian-He;  Chen, Xiaoming
收藏  |  浏览/下载：23/0  |  提交时间：2025/12/03
Logic  Computer architecture  Integrated circuit interconnections  Hardware  Routing  Circuits  Table lookup  Decoding  Performance evaluation  Logic gates  Processing in memory  resistive random-access memory (RRAM)  software-hardware co-design  ternary content-addressable memory (TCAM)  
DNA: A General Dynamic Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON COMPUTERS, 2025, 卷号: 74, 期号: 9, 页码: 3210-3222
作者:  Liu, Lian;  Yu, Jinxin;  Wang, Mengdi;  Li, Xiaowei;  Han, Yinhe;  Wang, Ying
收藏  |  浏览/下载：21/0  |  提交时间：2025/12/03
Dynamic scheduling  Artificial neural networks  DNA  Processor scheduling  Loading  Prefetching  Runtime  Costs  Switches  Optimization  Dynamic NN  NPU design  accelerator  
Resister: A Resilient Interposer Architecture for Chiplet to Mitigate Timing Side-Channel Attacks 期刊论文
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2025, 卷号: 30, 期号: 5, 页码: 23
作者:  Wang, Xinrui;  Feng, Lang;  Wang, Yujie;  Xu, Taotao;  Han, Yinhe;  Wang, Zhongfeng
收藏  |  浏览/下载：2/0  |  提交时间：2026/05/25
Chiplet  interposer  timing side-channel attack  mitigate