中国科学院计算技术研究所机构知识库

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限定条件	作者：Han, Yinhe    第一作者    资助项目：National Natural Science Foundation of China[61432017]

已选(0)清除 条数/页：5101520253035404550556065707580859095100   排序方式：请选择期刊影响因子升序期刊影响因子降序发表日期升序发表日期降序提交时间升序提交时间降序作者升序作者降序WOS被引频次升序WOS被引频次降序题名升序题名降序
	Architecting Effectual Computation for Machine Learning Accelerators 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667 作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：88/0  |  提交时间：2020/12/10 Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits
	A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277 作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei 收藏  |  浏览/下载：67/0  |  提交时间：2019/12/10 Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)
	PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei 收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13 3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput
	VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870 作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei 收藏  |  浏览/下载：35/0  |  提交时间：2019/12/13 Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)