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STC-NAS: Fast neural architecture search with source-target consistency 期刊论文
NEUROCOMPUTING, 2022, 卷号: 497, 页码: 227-238
作者:  Sun, Zihao;  Hu, Yu;  Yang, Longxing;  Lu, Shun;  Mei, Jilin;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载：20/0  |  提交时间：2022/12/07
Neural architecture search  Consistency  Automatic  Jensen-Shannon divergence  
Architecting Effectual Computation for Machine Learning Accelerators 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 卷号: 39, 期号: 10, 页码: 2654-2667
作者:  Lu, Hang;  Zhang, Mingzhe;  Han, Yinhe;  Wang, Qi;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：88/0  |  提交时间：2020/12/10
Computational modeling  Throughput  Adders  Machine learning  Acceleration  Kernel  Computational efficiency  Accelerator architectures  neural network hardware  multiplying circuits  
Accelerating DNN-based 3D point cloud processing for mobile computing 期刊论文
SCIENCE CHINA-INFORMATION SCIENCES, 2019, 卷号: 62, 期号: 11, 页码: 11
作者:  Liu, Bosheng;  Chen, Xiaoming;  Han, Yinhe;  Li, Jiajun;  Xu, Haobo;  Li, Xiaowei
收藏  |  浏览/下载：225/0  |  提交时间：2019/12/10
deep neural network acceleration  point cloud data  neighbor point search  mobile robotics  hardware architecture  
Thread: Towards fine-grained precision reconfiguration in variable-precision neural network accelerator 期刊论文
IEICE ELECTRONICS EXPRESS, 2019, 卷号: 16, 期号: 14, 页码: 6
作者:  Zhang, Shichang;  Wang, Ying;  Chen, Xiaoming;  Han, Yinhe;  Wang, Yujie;  Li, Xiaowei
收藏  |  浏览/下载：77/0  |  提交时间：2019/12/10
DNN accelerator  variable bit-precision  bit-serial  bit-parallel  fine-grained precision  
PIMSim: A Flexible and Detailed Processing-in-Memory Simulator 期刊论文
IEEE COMPUTER ARCHITECTURE LETTERS, 2019, 卷号: 18, 期号: 1, 页码: 6-9
作者:  Xu, Sheng;  Chen, Xiaoming;  Wang, Ying;  Han, Yinhe;  Qian, Xuehai;  Li, Xiaowei
收藏  |  浏览/下载：80/0  |  提交时间：2019/04/03
Processing-in-memory  simulator  heterogeneous computing  memory system  
A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multiprocessors 期刊论文
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 卷号: 37, 期号: 6, 页码: 1265-1277
作者:  Wang, Ying;  Li, Huawei;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载：67/0  |  提交时间：2019/12/10
Cache  chip multiprocessor (CMP)  compression  memory hierarchy  network-on-chip (NoC)  
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 卷号: 25, 期号: 4, 页码: 1285-1296
作者:  Song, Lili;  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：70/0  |  提交时间：2019/12/12
Approximate computing  machine learning  neural network  spin toque transfer RAM (STT-RAM)  
EcoUp: Towards Economical Datacenter Upgrading 期刊论文
IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS, 2016, 卷号: 27, 期号: 7, 页码: 1968-1981
作者:  Yan, Guihai;  Ma, Jun;  Han, Yinhe;  Li, Xiaowei
收藏  |  浏览/下载：61/0  |  提交时间：2019/12/13
Datacenter upgrading  cost efficiency  performance prediction  recommender systems  collaborative filtering  
PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 5, 页码: 1613-1625
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Zhang, Lei;  Cheng, Yuanqing;  Li, Xiaowei
收藏  |  浏览/下载：53/0  |  提交时间：2019/12/13
3-D integration  IR-drop  phase-change memory (PCM)  through-silicon-via (TSV)  write throughput  
VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache 期刊论文
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 卷号: 24, 期号: 3, 页码: 858-870
作者:  Wang, Ying;  Han, Yinhe;  Li, Huawei;  Li, Xiaowei
收藏  |  浏览/下载：35/0  |  提交时间：2019/12/13
Cache design  fault tolerant  multi-V-dd  near-threshold voltage (NTV)  nonuniform cache access (NUCA)